1.9.2

Update

• Bug fix (as well as 1.8.3): Fixed a bug that a read/write request in AXI-slave interfaces can be dismissed.

Test environment

macOS 11.2.2

• Python 3.9.2
• Icarus Verilog 11.0
• Pyverilog 1.3.0
• numpy: 1.19.4

Ubuntu 20.04.2

• Python 3.7.7
• Icarus Verilog 10.1
• Pyverilog 1.3.0
• numpy: 1.20.1

1.8.3

Update

• Bug fix: Fixed a bug that a read/write request in AXI-slave interfaces can be dismissed.
• Updated Thread compiler (thread.compiler) for Python 3.9.

Test environment

macOS 11.2.2

• Python 3.9.2
• Icarus Verilog 11.0
• Pyverilog 1.3.0
• numpy: 1.19.4

Ubuntu 20.04.2

• Python 3.7.7
• Icarus Verilog 10.1
• Pyverilog 1.3.0
• numpy: 1.20.1

1.9.1

Update

• Bug fix of stream.Div and stream.Mod.
• Updated the corresponding test codes for stream.Div and stream.Mod.

Test environment

macOS 10.15.7

• Python 3.9.1
• Icarus Verilog 11.0
• Pyverilog 1.3.0

Ubuntu 18.04.5

• Python 3.7.7
• Icarus Verilog 10.1
• Pyverilog 1.3.0

1.9.0

Update

• Stream support FIFO-based input/output in addition to conventional RAM. Since a FIFO can be empty, Stream currently has a pipeline stall mechanism. Stream can be used together with AXI-Stream via FIFO. Please see examples/thread_stream_axi_stream_fifo_ipxact.
• In Stream, A mechanism for multi-cycle operators (II > 1) is implemented based on the pipeline stall mechanism. ReduceMul and ReduceDiv are multi-cycle operators which require multiple clock cycles for each step. If you want to define a multi-cycle behavior based on multiple single-cycle operators, please use substream_multicycle.
• In Stream, Non-DAG structure with a loop-back is supported by stream.Consumer and stream.Producer. Please see tests//extension/thread_/stream_producer_consumer.
• In Veriloggen Core and Stream, Probe for easy debugging is introduced. By adding a name prefix, a target signal can be easily identified in a waveform viewer.
• In Stream, The naming rules for Delay, Prev, Alias of Stream operators are updated. To easily identify the origin of the variable, the name includes the original variable name.
• stream.Counter can accept Variable as initval to programmable initial (reset) values of registers.
• stream.LineBuffer is implemented.
• Stream supports the conditional termination of execution. Please use strm.terminate(condition).
• In Stream, constant is renamed as parameter.
• On-chip RAM (BRAM) currently supports the enable control for the pipeline stall mechanism.
• bit_length() method is renamed as get_width().

Test environment

macOS 10.15.7

• Python 3.9.1
• Icarus Verilog 11.0
• Pyverilog 1.3.0

Ubuntu 18.04.5

• Python 3.7.7
• Icarus Verilog 10.1
• Pyverilog 1.3.0

1.8.2

Update

• AXI-Stream is supported.
• The implementation of stream.Counter is renewed, so that some bugs of stream.Counter are fixed.
• stream.Sync operator that synchronize explicitly the start stages of input variables is added.
• stream.ForwardDest and stream.ForwardSource for data forwarding between stream.read_RAM and stream.write_RAM is added. This operator is required to realize a read_modify_write_RAM operator.
• stream.Alias is added.
• stream.ReduceMax, ReduceMin, ReduceArgMax, and ReduceArgMin are added for NNgen.

Test environment

macOS 10.15.4

• Python 3.7.7
• Icarus Verilog 10.3
• Pyverilog 1.2.1

Ubuntu 18.04.4

• Python 3.7.2
• Icarus Verilog 10.1
• Pyverilog 1.2.1

1.8.1

Update

• Some template text files for IP-XACT were not included in the tar file for PyPI in the previous version. This version include a bug fix such the files are included.
• README.rst was removed. Instead README.md is used for PyPI description.
• Memory image creation methods were optimized and accelerated by using numpy.

Test environment

macOS 10.15.1

• Python 3.7.5
• Icarus Verilog 10.3
• Pyverilog 1.2.0

Ubuntu 18.04.3

• Python 3.6.8
• Icarus Verilog 10.1
• Pyverilog 1.2.0

1.8.0

Update

• veriloggen.core: N-dimension array is supported for almost variable types.
• veriloggen.stream: Accumulator registers in stream pipelines are kept after executions for continuous sequent executions.
• veriloggen.types.axi: The bit-width of AxLOCK is changed to 1 according to the AXI4 specification.

Test environment

macOS 10.15.1

• Python 3.7.5
• Icarus Verilog 10.3
• Pyverilog 1.2.0

Ubuntu 18.04.3

• Python 3.6.8
• Icarus Verilog 10.1
• Pyverilog 1.2.0

1.7.3

Update

• A bug fix of generate-scope handling in veriloggen.from_verilog and veriloggen.resolver.

Test environment

Mac OSX 10.14.6

• Python 3.7.4
• Icarus Verilog 10.2
• Pyverilog 1.1.4

Ubuntu 18.04.3

• Python 3.6.8
• Icarus Verilog 10.1
• Pyverilog 1.1.4

1.7.2

Update

• stream.ToExtern/FromExtern: External behavior definition in RTL.
• stream.Reg: External Reg that can be accessed from RTL/Thread.
• stream.ReadRAM/WriteRAM: Indirect RAM access interfaces
• Stream.source_join_and_run: fast handshake method for sequent join and re-run.

Test environment

Mac OSX 10.14.6

• Python 3.7.4
• Icarus Verilog 10.2
• Pyverilog 1.1.4

Ubuntu 18.04.2

• Python 3.6.8
• Icarus Verilog 10.1
• Pyverilog 1.1.4

1.7.1

Update

• Changed the default values of AxCACHE, AxPROT, and AxUSER in AXI interfaces (veriloggen.types.axi, veriloggen.thread)

Test environment

Mac OSX 10.14.4

• Python 3.7.3
• Icarus Verilog 10.2
• Pyverilog 1.1.4

Ubuntu 18.04.2

• Python 3.6.7
• Icarus Verilog 10.1
• Pyverilog 1.1.4