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1.8.2
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@shtaxxx shtaxxx released this 03 May 13:09
· 505 commits to master since this release
1.8.2
e61f28e

Update

  • AXI-Stream is supported.
  • The implementation of stream.Counter is renewed, so that some bugs of stream.Counter are fixed.
  • stream.Sync operator that synchronize explicitly the start stages of input variables is added.
  • stream.ForwardDest and stream.ForwardSource for data forwarding between stream.read_RAM and stream.write_RAM is added. This operator is required to realize a read_modify_write_RAM operator.
  • stream.Alias is added.
  • stream.ReduceMax, ReduceMin, ReduceArgMax, and ReduceArgMin are added for NNgen.

Test environment

macOS 10.15.4

  • Python 3.7.7
  • Icarus Verilog 10.3
  • Pyverilog 1.2.1

Ubuntu 18.04.4

  • Python 3.7.2
  • Icarus Verilog 10.1
  • Pyverilog 1.2.1
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