Skip to content

1.7.2
Compare
Choose a tag to compare
@shtaxxx shtaxxx released this 25 Jul 06:56
· 640 commits to master since this release
1.7.2
fa3ec32

Update

  • stream.ToExtern/FromExtern: External behavior definition in RTL.
  • stream.Reg: External Reg that can be accessed from RTL/Thread.
  • stream.ReadRAM/WriteRAM: Indirect RAM access interfaces
  • Stream.source_join_and_run: fast handshake method for sequent join and re-run.

Test environment

Mac OSX 10.14.6

  • Python 3.7.4
  • Icarus Verilog 10.2
  • Pyverilog 1.1.4

Ubuntu 18.04.2

  • Python 3.6.8
  • Icarus Verilog 10.1
  • Pyverilog 1.1.4
Assets 2
Loading