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shtaxxxshtaxxx
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Merge branch 'fix_axislave_1.8.2-rc'
2 parents cf82f46 + db95fe0 commit 7464b3b

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27 files changed

+632
-169
lines changed

27 files changed

+632
-169
lines changed

‎examples/thread_add_ipxact/test_thread_add_ipxact.py

Lines changed: 23 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -731,7 +731,7 @@
731731
(_tmp_5 == 6)? _saxi_resetval_6 :
732732
(_tmp_5 == 7)? _saxi_resetval_7 : 'hx;
733733
reg _saxi_cond_0_1;
734-
assign saxi_wready = _saxi_register_fsm == 2;
734+
assign saxi_wready = _saxi_register_fsm == 3;
735735
reg [32-1:0] th_add;
736736
localparam th_add_init = 0;
737737
reg signed [32-1:0] _th_add_a_0;
@@ -834,28 +834,28 @@
834834
_saxi_register_7 <= _tmp_8;
835835
_saxi_flag_7 <= 0;
836836
end
837-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
837+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
838838
_saxi_register_0 <= saxi_wdata;
839839
end
840-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
840+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
841841
_saxi_register_1 <= saxi_wdata;
842842
end
843-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
843+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
844844
_saxi_register_2 <= saxi_wdata;
845845
end
846-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
846+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
847847
_saxi_register_3 <= saxi_wdata;
848848
end
849-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
849+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
850850
_saxi_register_4 <= saxi_wdata;
851851
end
852-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
852+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
853853
_saxi_register_5 <= saxi_wdata;
854854
end
855-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
855+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
856856
_saxi_register_6 <= saxi_wdata;
857857
end
858-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
858+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
859859
_saxi_register_7 <= saxi_wdata;
860860
end
861861
if((_saxi_register_0 == 1) && (th_add == 2) && 1) begin
@@ -959,6 +959,7 @@
959959
960960
localparam _saxi_register_fsm_1 = 1;
961961
localparam _saxi_register_fsm_2 = 2;
962+
localparam _saxi_register_fsm_3 = 3;
962963
963964
always @(posedge CLK) begin
964965
if(RST) begin
@@ -973,16 +974,26 @@
973974
_saxi_register_fsm <= _saxi_register_fsm_1;
974975
end
975976
if(_tmp_1) begin
976-
_saxi_register_fsm <= _saxi_register_fsm_2;
977+
_saxi_register_fsm <= _saxi_register_fsm_3;
977978
end
978979
end
979980
_saxi_register_fsm_1: begin
980-
if(saxi_rready || !saxi_rvalid) begin
981+
if(saxi_rready && saxi_rvalid) begin
981982
_saxi_register_fsm <= _saxi_register_fsm_init;
982983
end
984+
if((saxi_rready || !saxi_rvalid) && !(saxi_rready && saxi_rvalid)) begin
985+
_saxi_register_fsm <= _saxi_register_fsm_2;
986+
end
983987
end
984988
_saxi_register_fsm_2: begin
985-
_saxi_register_fsm <= _saxi_register_fsm_init;
989+
if(saxi_rready && saxi_rvalid) begin
990+
_saxi_register_fsm <= _saxi_register_fsm_init;
991+
end
992+
end
993+
_saxi_register_fsm_3: begin
994+
if(saxi_wready && saxi_wvalid) begin
995+
_saxi_register_fsm <= _saxi_register_fsm_init;
996+
end
986997
end
987998
endcase
988999
end

‎examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py

Lines changed: 23 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1302,7 +1302,7 @@
13021302
(_tmp_5 == 6)? _saxi_resetval_6 :
13031303
(_tmp_5 == 7)? _saxi_resetval_7 : 'hx;
13041304
reg _saxi_cond_0_1;
1305-
assign saxi_wready = _saxi_register_fsm == 2;
1305+
assign saxi_wready = _saxi_register_fsm == 3;
13061306
13071307
reg [31:0] sum;
13081308
always @(posedge CLK) begin
@@ -1728,28 +1728,28 @@
17281728
_saxi_register_7 <= _tmp_8;
17291729
_saxi_flag_7 <= 0;
17301730
end
1731-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
1731+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
17321732
_saxi_register_0 <= saxi_wdata;
17331733
end
1734-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
1734+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
17351735
_saxi_register_1 <= saxi_wdata;
17361736
end
1737-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
1737+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
17381738
_saxi_register_2 <= saxi_wdata;
17391739
end
1740-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
1740+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
17411741
_saxi_register_3 <= saxi_wdata;
17421742
end
1743-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
1743+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
17441744
_saxi_register_4 <= saxi_wdata;
17451745
end
1746-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
1746+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
17471747
_saxi_register_5 <= saxi_wdata;
17481748
end
1749-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
1749+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
17501750
_saxi_register_6 <= saxi_wdata;
17511751
end
1752-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
1752+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
17531753
_saxi_register_7 <= saxi_wdata;
17541754
end
17551755
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 1) begin
@@ -1821,6 +1821,7 @@
18211821
18221822
localparam _saxi_register_fsm_1 = 1;
18231823
localparam _saxi_register_fsm_2 = 2;
1824+
localparam _saxi_register_fsm_3 = 3;
18241825
18251826
always @(posedge CLK) begin
18261827
if(RST) begin
@@ -1835,16 +1836,26 @@
18351836
_saxi_register_fsm <= _saxi_register_fsm_1;
18361837
end
18371838
if(_tmp_1) begin
1838-
_saxi_register_fsm <= _saxi_register_fsm_2;
1839+
_saxi_register_fsm <= _saxi_register_fsm_3;
18391840
end
18401841
end
18411842
_saxi_register_fsm_1: begin
1842-
if(saxi_rready || !saxi_rvalid) begin
1843+
if(saxi_rready && saxi_rvalid) begin
18431844
_saxi_register_fsm <= _saxi_register_fsm_init;
18441845
end
1846+
if((saxi_rready || !saxi_rvalid) && !(saxi_rready && saxi_rvalid)) begin
1847+
_saxi_register_fsm <= _saxi_register_fsm_2;
1848+
end
18451849
end
18461850
_saxi_register_fsm_2: begin
1847-
_saxi_register_fsm <= _saxi_register_fsm_init;
1851+
if(saxi_rready && saxi_rvalid) begin
1852+
_saxi_register_fsm <= _saxi_register_fsm_init;
1853+
end
1854+
end
1855+
_saxi_register_fsm_3: begin
1856+
if(saxi_wready && saxi_wvalid) begin
1857+
_saxi_register_fsm <= _saxi_register_fsm_init;
1858+
end
18481859
end
18491860
endcase
18501861
end

‎examples/thread_ipxact/test_thread_ipxact.py

Lines changed: 19 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -660,7 +660,7 @@
660660
(_tmp_5 == 2)? _saxi_resetval_2 :
661661
(_tmp_5 == 3)? _saxi_resetval_3 : 'hx;
662662
reg _saxi_cond_0_1;
663-
assign saxi_wready = _saxi_register_fsm == 2;
663+
assign saxi_wready = _saxi_register_fsm == 3;
664664
reg [32-1:0] th_blink;
665665
localparam th_blink_init = 0;
666666
reg signed [32-1:0] _th_blink_size_0;
@@ -736,16 +736,16 @@
736736
_saxi_register_3 <= _tmp_8;
737737
_saxi_flag_3 <= 0;
738738
end
739-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
739+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
740740
_saxi_register_0 <= saxi_wdata;
741741
end
742-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
742+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
743743
_saxi_register_1 <= saxi_wdata;
744744
end
745-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
745+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
746746
_saxi_register_2 <= saxi_wdata;
747747
end
748-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
748+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
749749
_saxi_register_3 <= saxi_wdata;
750750
end
751751
if((_saxi_register_0 == 1) && (th_blink == 2) && 1) begin
@@ -801,6 +801,7 @@
801801
802802
localparam _saxi_register_fsm_1 = 1;
803803
localparam _saxi_register_fsm_2 = 2;
804+
localparam _saxi_register_fsm_3 = 3;
804805
805806
always @(posedge CLK) begin
806807
if(RST) begin
@@ -815,16 +816,26 @@
815816
_saxi_register_fsm <= _saxi_register_fsm_1;
816817
end
817818
if(_tmp_1) begin
818-
_saxi_register_fsm <= _saxi_register_fsm_2;
819+
_saxi_register_fsm <= _saxi_register_fsm_3;
819820
end
820821
end
821822
_saxi_register_fsm_1: begin
822-
if(saxi_rready || !saxi_rvalid) begin
823+
if(saxi_rready && saxi_rvalid) begin
823824
_saxi_register_fsm <= _saxi_register_fsm_init;
824825
end
826+
if((saxi_rready || !saxi_rvalid) && !(saxi_rready && saxi_rvalid)) begin
827+
_saxi_register_fsm <= _saxi_register_fsm_2;
828+
end
825829
end
826830
_saxi_register_fsm_2: begin
827-
_saxi_register_fsm <= _saxi_register_fsm_init;
831+
if(saxi_rready && saxi_rvalid) begin
832+
_saxi_register_fsm <= _saxi_register_fsm_init;
833+
end
834+
end
835+
_saxi_register_fsm_3: begin
836+
if(saxi_wready && saxi_wvalid) begin
837+
_saxi_register_fsm <= _saxi_register_fsm_init;
838+
end
828839
end
829840
endcase
830841
end

‎examples/thread_memcpy_ipxact/test_thread_memcpy_ipxact.py

Lines changed: 23 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1299,7 +1299,7 @@
12991299
(_tmp_5 == 6)? _saxi_resetval_6 :
13001300
(_tmp_5 == 7)? _saxi_resetval_7 : 'hx;
13011301
reg _saxi_cond_0_1;
1302-
assign saxi_wready = _saxi_register_fsm == 2;
1302+
assign saxi_wready = _saxi_register_fsm == 3;
13031303
reg [32-1:0] th_memcpy;
13041304
localparam th_memcpy_init = 0;
13051305
reg signed [32-1:0] _th_memcpy_copy_bytes_0;
@@ -1711,28 +1711,28 @@
17111711
_saxi_register_7 <= _tmp_8;
17121712
_saxi_flag_7 <= 0;
17131713
end
1714-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
1714+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
17151715
_saxi_register_0 <= saxi_wdata;
17161716
end
1717-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
1717+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
17181718
_saxi_register_1 <= saxi_wdata;
17191719
end
1720-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
1720+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
17211721
_saxi_register_2 <= saxi_wdata;
17221722
end
1723-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
1723+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
17241724
_saxi_register_3 <= saxi_wdata;
17251725
end
1726-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
1726+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
17271727
_saxi_register_4 <= saxi_wdata;
17281728
end
1729-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
1729+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
17301730
_saxi_register_5 <= saxi_wdata;
17311731
end
1732-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
1732+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
17331733
_saxi_register_6 <= saxi_wdata;
17341734
end
1735-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
1735+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
17361736
_saxi_register_7 <= saxi_wdata;
17371737
end
17381738
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 1) begin
@@ -1804,6 +1804,7 @@
18041804
18051805
localparam _saxi_register_fsm_1 = 1;
18061806
localparam _saxi_register_fsm_2 = 2;
1807+
localparam _saxi_register_fsm_3 = 3;
18071808
18081809
always @(posedge CLK) begin
18091810
if(RST) begin
@@ -1818,16 +1819,26 @@
18181819
_saxi_register_fsm <= _saxi_register_fsm_1;
18191820
end
18201821
if(_tmp_1) begin
1821-
_saxi_register_fsm <= _saxi_register_fsm_2;
1822+
_saxi_register_fsm <= _saxi_register_fsm_3;
18221823
end
18231824
end
18241825
_saxi_register_fsm_1: begin
1825-
if(saxi_rready || !saxi_rvalid) begin
1826+
if(saxi_rready && saxi_rvalid) begin
18261827
_saxi_register_fsm <= _saxi_register_fsm_init;
18271828
end
1829+
if((saxi_rready || !saxi_rvalid) && !(saxi_rready && saxi_rvalid)) begin
1830+
_saxi_register_fsm <= _saxi_register_fsm_2;
1831+
end
18281832
end
18291833
_saxi_register_fsm_2: begin
1830-
_saxi_register_fsm <= _saxi_register_fsm_init;
1834+
if(saxi_rready && saxi_rvalid) begin
1835+
_saxi_register_fsm <= _saxi_register_fsm_init;
1836+
end
1837+
end
1838+
_saxi_register_fsm_3: begin
1839+
if(saxi_wready && saxi_wvalid) begin
1840+
_saxi_register_fsm <= _saxi_register_fsm_init;
1841+
end
18311842
end
18321843
endcase
18331844
end

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