1.9.0

Update

• Stream support FIFO-based input/output in addition to conventional RAM. Since a FIFO can be empty, Stream currently has a pipeline stall mechanism. Stream can be used together with AXI-Stream via FIFO. Please see examples/thread_stream_axi_stream_fifo_ipxact.
• In Stream, A mechanism for multi-cycle operators (II > 1) is implemented based on the pipeline stall mechanism. ReduceMul and ReduceDiv are multi-cycle operators which require multiple clock cycles for each step. If you want to define a multi-cycle behavior based on multiple single-cycle operators, please use substream_multicycle.
• In Stream, Non-DAG structure with a loop-back is supported by stream.Consumer and stream.Producer. Please see tests//extension/thread_/stream_producer_consumer.
• In Veriloggen Core and Stream, Probe for easy debugging is introduced. By adding a name prefix, a target signal can be easily identified in a waveform viewer.
• In Stream, The naming rules for Delay, Prev, Alias of Stream operators are updated. To easily identify the origin of the variable, the name includes the original variable name.
• stream.Counter can accept Variable as initval to programmable initial (reset) values of registers.
• stream.LineBuffer is implemented.
• Stream supports the conditional termination of execution. Please use strm.terminate(condition).
• In Stream, constant is renamed as parameter.
• On-chip RAM (BRAM) currently supports the enable control for the pipeline stall mechanism.
• bit_length() method is renamed as get_width().

Test environment

macOS 10.15.7

• Python 3.9.1
• Icarus Verilog 11.0
• Pyverilog 1.3.0

Ubuntu 18.04.5

• Python 3.7.7
• Icarus Verilog 10.1
• Pyverilog 1.3.0