Releases: PyHDI/veriloggen
Releases · PyHDI/veriloggen
1.0.4
Update
- Submodule functionality is improved. Parameter and localparams can be correctly handled in a parent module.
- Read/Write dataflow behavior of RAM is update. Sign options of some data-related signals are changed to 'signed=True', so that negative values can can be handled correctly.
- AxiMemoryModel supports read/write methods to access the register array of the model from the simulation thread.
Test environment
Mac OSX 10.12.6
- Python 3.6.2
- Python 2.7.10
- Icarus Verilog 0.9.7
- Pyverilog 1.1.1
- IPgen 0.3.1
Ubuntu 16.04
- Python 3.5.2
- Python 2.7.12
- Icarus Verilog 0.9.7
- Pyverilog 1.1.1
- IPgen 0.3.1
1.0.3
Update
- veriloggen.types.ipcore is updated for the latest IPgen.
Test environment
Mac OSX 10.12.6
- Python 3.6.2
- Python 2.7.10
- Icarus Verilog 0.9.7
- Pyverilog 1.1.1
- IPgen 0.3.1
Ubuntu 16.04
- Python 3.5.2
- Python 2.7.12
- Icarus Verilog 0.9.7
- Pyverilog 1.1.1
- IPgen 0.3.1
1.0.2
Update
- veriloggen.thread.Stream: read_parameter(obj, size, point=0, signed=True) is a stream generator from a parameter register.
Test environment
Mac OSX 10.12.6
- Python 3.6.2
- Python 2.7.10
- Icarus Verilog 0.9.7
- Pyverilog 1.1.1
- IPgen 0.3.0
Ubuntu 16.04
- Python 3.5.2
- Python 2.7.12
- Icarus Verilog 0.9.7
- Pyverilog 1.1.1
- IPgen 0.3.0
1.0.1
Update
- Default sign of dataflow operators is changed to 'signed' from 'unsigned'.
Test environment
Mac OSX 10.12.6
- Python 3.6.2
- Python 2.7.10
- Icarus Verilog 0.9.7
- Pyverilog 1.1.1
- IPgen 0.3.0
Ubuntu 16.04
- Python 3.5.2
- Python 2.7.12
- Icarus Verilog 0.9.7
- Pyverilog 1.1.1
- IPgen 0.3.0
1.0.0
Update
- This is a first major release. This version includes numerous big updates of all components from the previous version.
Test environment
Mac OSX 10.12.6
- Python 3.6.2
- Python 2.7.10
- Icarus Verilog 0.9.7
- Pyverilog 1.1.0
- IPgen 0.3.0
Ubuntu 16.04
- Python 3.5.2
- Python 2.7.12
- Icarus Verilog 0.9.7
- Pyverilog 1.1.0
- IPgen 0.3.0
0.8.3
0.8.2
0.8.1
Update
A portable IP-core synthesis is now supported. You can easily create an original IP-core just by writing Python!
- AXI-slave interface and memory-mapped register are supported
- AXI-master in veriloggen.thread supports read/write method to access to a memory-mapped register easily
- AXI4/Avalon IP-core packager support via IPgen is added
- Synopsys VCS (very fast commercial Verilog simulator) support is added
Test environment
Mac OSX 10.12.4
- python 3.6.1
- python 2.7.13
- icarus verilog 0.9.7
Ubuntu 16.04
- python 3.5.2
- python 2.7.12
- icarus verilog 0.9.7
0.8.0
This is the first version that includes veriloggen.thread, a tightly-coupled high-level synthesis compiler embedded within Veriloggen HDL.
veriloggen.thread
- Tightly-coupled high-level synthesis compiler emedded within Veriloggen HDL.
- This compiler supports tightly-coupled interaction between RTL definitions by Veriloggen HDL, embedding RTL definitions in HLS definitions (intrinsic), and concurrent multithreading.
- Additionally, this supports the stream processing via veriloggen.dataflow for high performance processing.
- Please see veriloggen/tests/extensions/threads_/ and veriloggen/examples/ to find many examples.
0.7.0
Update
This version includes some challenging updates of hardware interface abstractions.
- veriloggen.types: Abstractions of frequent-appeared interfaces, such as on-chip memory and on-chip bus, are implemented. Please see the test codes in "tests/extension/types_/".
- veriloggen.dataflow.DataflowManager is added: it manages dataflow variable implementations on an existing Module objects and automatically synthesizes native signal objects belonging to the Module.
- veriloggen.dataflow supports read/write operations from outside of dataflow definitions.
- veriloggen.FSM and Seq support more human-readable assignment definitions by the object call as a method. Please see the test codes in "tests/extension/fsm_/" and "tests/extension/seq_/".
- The feature of existing Verilog importation has been improved.
- Fundamental objects in veriloggen.core.types supports the bit_length() method to return its bit width.
Test environment
Mac OSX 10.11.6 (El Capitan)
- python 3.5.2
- python 2.7.12
Ubuntu 16.04 LTS
- python 3.5.2
- python 2.7.12