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[fud] Simplify and centralize fud configuration for Xilinx tools
C: FPGA
Changes for the FPGA backend
C: fud
Calyx Driver
S: Available
Can be worked upon
#856
opened Jan 6, 2022 by
sampsyo
Reducing control fan-out
C: Calyx
Extension or change to the Calyx IL
S: Available
Can be worked upon
Rename output ports on Calyx's standard library
S: Available
Can be worked upon
div_pipe
s.
C: Library
#489
opened Apr 18, 2021 by
cgyurgyik
Testing the Relay frontend against a developed infrastructure.
C: Relay
Relay-to-FuTIL compiler
#494
opened Apr 27, 2021 by
cgyurgyik
exp
operator producing negative values when x
is a large negative number.
S: Available
#505
opened May 8, 2021 by
cgyurgyik
resource-sharing
: Sharing generates invalid verilog
C: Calyx
#532
opened Jun 8, 2021 by
rachitnigam
tdcc
: Invalid code generated when done
depends on input signal
Type: Bug
#621
opened Aug 2, 2021 by
rachitnigam
tdcc
: Incorrect early transitions in presence of par
C: Calyx
#662
opened Sep 10, 2021 by
rachitnigam
[fud] Uniquely named stages
C: fud
Calyx Driver
S: Needs Triage
Issue needs some thinking
#751
opened Oct 27, 2021 by
rachitnigam
[library] Remove blocking statements.
C: Library
Calyx's standard library
good first issue
Good issue to start contributing on Calyx
S: Available
Can be worked upon
#754
opened Oct 28, 2021 by
cgyurgyik
Add icarus-verilog to test suite.
C: Calyx
Extension or change to the Calyx IL
S: Available
Can be worked upon
#755
opened Oct 28, 2021 by
cgyurgyik
register-unsharing
: check if it works with combinational groups and ports used in conditions
C: Calyx
#831
opened Dec 25, 2021 by
rachitnigam
Unstable reads
S: Available
Can be worked upon
Type: Paper cut
Spurious or confusing errors
Type: Pass
Proposal to implement a pass
#304
opened Dec 10, 2020 by
rachitnigam
Parameterize systolic generator to use different PE
C: Systolic Array
Systolic array generator
S: Available
Can be worked upon
#836
opened Dec 27, 2021 by
rachitnigam
Parallel assignment asserts do not work with icarus verilog
S: Needs Triage
Issue needs some thinking
#859
opened Jan 7, 2022 by
rachitnigam
[IR] Changes to compiler internals
S: Available
Can be worked upon
done
condition should not be an assignment
C: Internal
#864
opened Jan 11, 2022 by
rachitnigam
[fud] State/stage conflation confuses implied state detection
C: fud
Calyx Driver
S: Available
Can be worked upon
#867
opened Jan 13, 2022 by
rachitnigam
comb-localize
: Inlining combinational continuous assignments into groups
C: calyx-opt
#870
opened Jan 13, 2022 by
rachitnigam
Xilinx toolchain
C: FPGA
Changes for the FPGA backend
C: fud
Calyx Driver
Type: Tracker
Track various tasks
#876
opened Jan 15, 2022 by
sampsyo
5 of 8 tasks
Proposal: Remove multi-dimensional memories from core primitives
C: Library
Calyx's standard library
S: Available
Can be worked upon
#907
opened Feb 10, 2022 by
rachitnigam
Pipeline multiply and other primitives
C: Library
Calyx's standard library
S: Needs Triage
Issue needs some thinking
#928
opened Feb 21, 2022 by
mikeurbach
-d <alias>
disables all instances of the pass invocation
C: Calyx
#985
opened Apr 25, 2022 by
rachitnigam
Invoke in presence of multiple go done signals
C: Calyx
Extension or change to the Calyx IL
S: Discussion needed
Issues blocked on discussion
#986
opened Apr 25, 2022 by
rachitnigam
[docs] Extend language tutorial to demonstrate Documentation to add/improve
S: Available
Can be worked upon
invoke
statements
C: Docs
#988
opened Apr 26, 2022 by
rachitnigam
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Updated in the last three days: updated:>2025-03-06.