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When performing logical optimization, the "if" command of ABC mistakenly simplified a complex combinational logic signal

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5459 In YosysHQ/yosys;

· Q-Elvis opened on Nov 3, 2025

Synthesis causing branch instructions to misbehave on RISC-V CPU

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5457 In YosysHQ/yosys;

· mivuzu opened on Nov 3, 2025

LibertyParser fails on latch enable with parens, but no enclosing double quotes

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5451 In YosysHQ/yosys;

· jeffng-or opened on Oct 30, 2025

abc -dress fails with status 86 when retiming

ABC

dependencies

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5432 In YosysHQ/yosys;

· leeway64 opened on Oct 17, 2025

synth command produces a non-equivalent circuit for a complex, fuzzed Verilog design

ABC

bug

discussneeds further discussion on the YosysHQ discourse (https://yosyshq.discourse.group)needs further discussion on the YosysHQ discourse (https://yosyshq.discourse.group)

documentation

fuzzerFuzzer generated issueFuzzer generated issue

Status: Open.

#5428 In YosysHQ/yosys;

· Q-Elvis opened on Oct 15, 2025

Selection syntax doesn't understand escaping

bug

Status: Open.

#5414 In YosysHQ/yosys;

· widlarizer opened on Oct 9, 2025

BRAM initialization error

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5409 In YosysHQ/yosys;

· RemyCiterin opened on Oct 7, 2025

Interface synthesis bug: Logic missing from main evaluation path ?

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5405 In YosysHQ/yosys;

· toby-bro opened on Oct 2, 2025

autoname may be inefficient for large circuits

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5394 In YosysHQ/yosys;

· KrystalDelusion opened on Sep 26, 2025

Support mixed input/output in cutpoint handling of inout

Status: Open.

#5383 In YosysHQ/yosys;

· KrystalDelusion opened on Sep 23, 2025

cxxrtl: -O1 optimisation unbuffers wires too permissively

cxxrtl

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5371 In YosysHQ/yosys;

· toby-bro opened on Sep 21, 2025

Interface and modport support bug ?

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

SystemVerilogIssues and questions related to SystemVerilogIssues and questions related to SystemVerilog

Status: Open.

#5366 In YosysHQ/yosys;

· toby-bro opened on Sep 19, 2025