BRAM initialization error

[RemyCiterin]

Version

Yosys 0.44 (git sha1 80ba43d, g++ 13.3.0 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

The Top.v file instantiate a BRAM initialized using Mem.hex and read the 3th byte at the address 1:

module mkTop (
  input clk100mhz, // 100 MHZ clock
  input reset,
  input [3:0] btn,

  output [7:0] led
);

  wire [31:0] DO;

  BlockRAM#(
    .ADDR_WIDTH(12),
    .DATA_WIDTH(32),
    .INIT_FILE("Mem.hex")
  ) blockRAM (
    .CLK(clk100mhz),
    .DI(32'hxxxxxxxx),
    .ADDR(12'h001),
    .WE(1'b0),
    .RE(1'b1),
    .DO(DO)
  );

  assign led = DO[23:16];
endmodule

and here is my wrapper for the BRAM (copied from https://github.com/blarney-lang/blarney/blob/master/Verilog/BlockRAM.v):

// Single-port block RAM
// =====================

module BlockRAM (
  CLK,     // Clock
  DI,      // Data in
  ADDR,    // Read address
  WE,      // Write enable
  RE,      // Read enable
  DO       // Data out
  );

  parameter ADDR_WIDTH = 1;
  parameter DATA_WIDTH = 1;
  parameter INIT_FILE  = "UNUSED";

  input  CLK;
  input  [DATA_WIDTH-1:0] DI;
  input  [ADDR_WIDTH-1:0] ADDR;
  input  WE, RE;
  output reg [DATA_WIDTH-1:0] DO;
  reg [DATA_WIDTH-1:0] RAM[2**ADDR_WIDTH-1:0];

  generate
    if (INIT_FILE != "UNUSED") begin
      initial $readmemh(INIT_FILE, RAM);
    end else begin
      integer i;
      initial
        for (i = 0; i < 2**ADDR_WIDTH; i=i+1)
          RAM[i] = 0;
    end
  endgenerate

  always @(posedge CLK)
  begin
    if (WE) begin
      RAM[ADDR] <= DI;
    end
    if (RE) begin
      if (WE) begin
        DO <= {DATA_WIDTH{1'hx}};
      end else begin
        DO <= RAM[ADDR];
      end
    end
  end

endmodule

Mem.hex.tar.gz

Then I generate the bytestream for a xilinx xc7a200tsbg484-1 using yosys+nextpnr.
I also created a small repo https://github.com/RemyCiterin/bram-bug-yosys-nextpnr-xilinx to reproduce the bug with this minimal example + dump the content of the BRAM

Expected Behavior

As I read the 3rd byte at the address 1 I expect the LED to display the number 0x82

Actual Behavior

Using a nexys-video board I observed the byte 0x80 with the LED. In fact it's not the only error I found, here are the 10 first values I observed:

00004297
d8808293
00005317
d8c10213
0062f863
00008023
00128293
fa60ece3
00005117
d3010013

and here are the 10 expected values from Mem.hex:

00004297    // raw_mem addr 00000000;  byte addr 00000000
d8828293    // raw_mem addr 00000001;  byte addr 00000004
00005317    // raw_mem addr 00000002;  byte addr 00000008
d8c30313    // raw_mem addr 00000003;  byte addr 0000000c
0062f863    // raw_mem addr 00000004;  byte addr 00000010
00028023    // raw_mem addr 00000005;  byte addr 00000014
00128293    // raw_mem addr 00000006;  byte addr 00000018
fe62ece3    // raw_mem addr 00000007;  byte addr 0000001c
00005117    // raw_mem addr 00000008;  byte addr 00000020
d7010113    // raw_mem addr 00000009;  byte addr 00000024

[Ravenslofty]

(you should update your Yosys; it's over a year old)

[RemyCiterin]

(you should update your Yosys; it's over a year old)

Thanks for the advice, I just tested with a more recent version (Yosys 0.55 (git sha1 60f126c, g++ 14.3.0 -fPIC -O3)) and it didn't work either.

[Ravenslofty]

I think my biggest question here is whether this is a Yosys bug or a nextpnr bug. Can you reproduce this by feeding Yosys output into Vivado?

[RemyCiterin]

I think my biggest question here is whether this is a Yosys bug or a nextpnr bug. Can you reproduce this by feeding Yosys output into Vivado?

I tried to use this command to generate the edif file from my repo:

yosys -q -p \
    "synth_xilinx -edif build/mkTop.edif -flatten -abc9 -arch xc7 -top mkTop2" \
    src/Top.v src/Top2.v simulation/Block*v simulation/pll_nexys_video.v Verilog/*.v 

then give the generated file to Vivado with the nexysvideo.xdc source, but I receive this error:

ERROR: [EDIF 20-83] Cannot find cell 'id00032' view 'VIEW_NETLIST' in library '' for instance 'blockRAM'

[KrystalDelusion]

Your source repo is incomplete:

ERROR: File `simulation/pll_nexys_video.v' not found or is a directory

Another suggestion is trying to write to the memory and making sure the data read back is consistent (just to confirm that it is the initialization that is the problem).

[RemyCiterin]

I added the file. I also changed the makefile, because I originally copied it from another project... now you need to do:

make yosys_minimal nextpnr program

to generate the minimal example with the LEDs and

make compile yosys_dump nextpnr program

to dump the BRAM contents via UART. I also added a Python script to remove the $scopeinfo because nextpnr-xilinx doesn't accept them (openXC7/nextpnr-xilinx#67)

[RemyCiterin]

I tested some write/read patterns today, and it didn't work either... In addition, I tested with multiple sizes of RAM and I obtained the following results:

• size 1 to 2^5: it works
• size 2^6 and 2^7: nextpnr-xilinx crash with "ERROR: Cannot pack unsupported primitive: RAM64X1S"
• size 2^8...2^11: it works
• size 2^12 (the size I used to test initialization): wrong values:
  I tried to write 0xffffffff into the first addresses of the RAM and I got:

fbfdfeff
fbfdfeff
fbfdfeff
...

• size 2^13, 2^14: it works
  Then I stopped testing because it was getting too long...
  I also changed the make compile target in favor of make compile_rw and make compile_init

[KrystalDelusion]

Thanks, that sounds like there might be a problem with the libmap files for the xc7.