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ABCdependenciespending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction
Description
Version
Yosys 0.58+74 (git sha1 272aa9c, clang++ 18.1.8 -fPIC -O3)
On which OS did this happen?
Linux
Reproduction Steps
Copy the following code into a file called synth.tcl:
yosys -import
read_verilog -sv OpenROAD-flow-scripts/flow/designs/src/gcd/gcd.v
synth -flatten
abc -dress -dff -D 1
Then, run the following:
git clone https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts.git
yosys synth.tcl
(Cloning OpenROAD-flow-scripts is only to get the gcd design)
If I include both -dff and -D 1 in the abc command, then I get ERROR: ABC failed with status 86.
Expected Behavior
The -dress flag should not throw an error when performing retiming.
Actual Behavior
The -dress flag throws the following error when performing retiming:
yosys-abc: src/base/abci/abcDress2.c:88: Aig_Man_t *abc::Aig_ManCreateDualOutputMiter(Aig_Man_t *, Aig_Man_t *): Assertion `Aig_ManCiNum(p1) == Aig_ManCiNum(p2)' failed.
yosys-abc: src/base/abci/abcDress2.c:88: Aig_Man_t *abc::Aig_ManCreateDualOutputMiter(Aig_Man_t *, Aig_Man_t *): Assertion `Aig_ManCiNum(p1) == Aig_ManCiNum(p2)' failed.
ERROR: ABC failed with status 86
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ABCdependenciespending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction