Add support for Renesas RA CEU (Capture Engine Unit) for RA8M1 and RA8D1

boards/renesas/ek_ra8d1/doc/index.rst

@@ -111,6 +111,14 @@ Supported Features
      |     OFF     |     OFF     |      OFF     |     OFF    |     OFF    |     ON     |     ON      |    OFF    |
      +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
 
+   - For using the Camera Expansion Port (J59) with the Camera, please set switch SW1 as following configuration:
+
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+     | SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C |
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+     |     OFF     |     OFF     |      ON     |     OFF    |     OFF    |     OFF     |     ON      |    OFF    |
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+
 .. warning::
 
    Do not enable SW1-4 and SW1-5 together

boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi

@@ -10,6 +10,7 @@
 			psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 14)>;
 			drive-strength = "medium";
 		};
+
 		group2 {
 			/* rx */
 			psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 15)>;
@@ -35,11 +36,26 @@
 		};
 	};
 
+	pwm3_default: pwm3_default {
+		group1 {
+			/* GTIOC3A */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 4, 3)>;
+			drive-strength = "medium";
+		};
+
+		group2 {
+			/* GTIOC3B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 4, 4)>;
+			drive-strength = "medium";
+		};
+	};
+
 	pwm7_default: pwm7_default {
 		group1 {
 			/* GTIOC7A */
 			psels = <RA_PSEL(RA_PSEL_GPT1, 10, 7)>;
 		};
+
 		group2 {
 			/* GTIOC7B */
 			psels = <RA_PSEL(RA_PSEL_GPT1, 10, 6)>;
@@ -208,6 +224,7 @@
 			<RA_PSEL(RA_PSEL_SDHI, 7, 0)>; /* SDWP */
 			drive-strength = "high";
 		};
+
 		group2 {
 			psels = <RA_PSEL(RA_PSEL_SDHI, 4, 0)>; /* SDCLK */
 			drive-strength = "highspeed-high";
@@ -289,4 +306,22 @@
 			drive-strength = "high";
 		};
 	};
+
+	ceu_default: ceu_default {
+		group1 {
+			/* CEU */
+			psels = <RA_PSEL(RA_PSEL_CEU, 4, 0)>, /* VIO_D0 */
+				<RA_PSEL(RA_PSEL_CEU, 4, 1)>, /* VIO_D1 */
+				<RA_PSEL(RA_PSEL_CEU, 4, 5)>, /* VIO_D2 */
+				<RA_PSEL(RA_PSEL_CEU, 4, 6)>, /* VIO_D3 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 0)>, /* VIO_D4 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 1)>, /* VIO_D5 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 2)>, /* VIO_D6 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 3)>, /* VIO_D7 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 8)>, /* VIO_CLK */
+				<RA_PSEL(RA_PSEL_CEU, 7, 9)>, /* VIO_HD */
+				<RA_PSEL(RA_PSEL_CEU, 7, 10)>; /* VIO_VD */
+			drive-strength = "high";
+		};
+	};
 };

boards/renesas/ek_ra8d1/ek_ra8d1.dts

@@ -12,6 +12,8 @@
 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
 #include <zephyr/dt-bindings/memory-controller/renesas,ra-sdram.h>
 #include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/gpio/dvp-20pin-connector.h>
+#include <zephyr/dt-bindings/pwm/pwm.h>
 #include "ek_ra8d1-pinctrl.dtsi"
 
 / {
@@ -78,6 +80,15 @@
 				<18 0 &ioporta 1 0>;	/* DISP_RST */
 	};
 
+	dvp_20pin_connector: dvp-20pin-connector {
+		compatible = "arducam,dvp-20pin-connector";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0x0 0x3f>;
+		gpio-map = <DVP_20PIN_PEN 0 &ioport7 4 0>,
+			   <DVP_20PIN_PDN 0 &ioport7 5 0>;
+	};
+
 	aliases {
 		led0 = &led1;
 		sw0 = &button0;
@@ -178,6 +189,10 @@
 	status = "okay";
 };
 
+&ioport7 {
+	status = "okay";
+};
+
 &ioporta {
 	status = "okay";
 };
@@ -226,6 +241,22 @@
 	};
 };
 
+&pwm3 {
+	pinctrl-0 = <&pwm3_default>;
+	pinctrl-names = "default";
+	interrupts = <51 12>, <52 12>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+
+	cam_clock: pwmclock {
+		compatible = "pwm-clock";
+		#clock-cells = <1>;
+		clock-frequency = <24000000>;
+		pwms = <&pwm3 0 PWM_KHZ(24000) PWM_POLARITY_NORMAL>;
+		status = "okay";
+	};
+};
+
 &pwm7 {
 	pinctrl-0 = <&pwm7_default>;
 	interrupts = <40 1>, <41 1>;
@@ -329,6 +360,17 @@
 	};
 };
 
+&ceu {
+	pinctrl-0 = <&ceu_default>;
+	pinctrl-names = "default";
+	interrupts = <53 12>;
+	interrupt-names = "ceui";
+	clocks = <&pclka MSTPC 16>, <&cam_clock 0>;
+	clock-names = "pclk", "cam-xclk";
+	burst-transfer = <256>;
+	status = "okay";
+};
+
 zephyr_lcdif: &lcdif {};
 
 zephyr_mipi_dsi: &mipi_dsi {};
@@ -337,6 +379,10 @@ renesas_mipi_i2c: &iic1 {};
 
 pmod_sd_shield: &sdhc1 {};
 
+dvp_20pin_i2c: &iic1 {};
+
+dvp_20pin_interface: &ceu {};
+
 &usbfs {
 	pinctrl-0 = <&usbfs_default>;
 	pinctrl-names = "default";

boards/renesas/ek_ra8d1/ek_ra8d1.yaml

@@ -14,4 +14,5 @@ supported:
   - usbd
   - display
   - counter
+  - video
 vendor: renesas

drivers/video/CMakeLists.txt

@@ -25,5 +25,6 @@ zephyr_library_sources_ifdef(CONFIG_VIDEO_EMUL_RX	video_emul_rx.c)
 zephyr_library_sources_ifdef(CONFIG_VIDEO_IMX335	imx335.c)
 zephyr_library_sources_ifdef(CONFIG_VIDEO_ST_MIPID02	video_st_mipid02.c)
 zephyr_library_sources_ifdef(CONFIG_VIDEO_STM32_DCMIPP	video_stm32_dcmipp.c)
+zephyr_library_sources_ifdef(CONFIG_VIDEO_RENESAS_RA_CEU    video_renesas_ra_ceu.c)
 
 zephyr_linker_sources(DATA_SECTIONS video.ld)

drivers/video/Kconfig

@@ -96,4 +96,6 @@ source "drivers/video/Kconfig.st_mipid02"
 
 source "drivers/video/Kconfig.stm32_dcmipp"
 
+source "drivers/video/Kconfig.renesas_ra_ceu"
+
 endif # VIDEO

drivers/video/Kconfig.renesas_ra_ceu

@@ -0,0 +1,19 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config VIDEO_RENESAS_RA_CEU
+	bool
+	default y
+	depends on DT_HAS_RENESAS_RA_CEU_ENABLED
+	select PINCTRL
+	select PWM
+	select USE_RA_FSP_CEU
+	help
+	  Enable driver for Renesas RA CEU.
+
+config VIDEO_RENESAS_BUFFER_SDRAM
+	bool "Allocate the video buffer into SDRAM"
+	depends on VIDEO_RENESAS_RA_CEU
+	select MEMC
+	help
+	  Allocate the video buffer into SDRAM