RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.

A Reconfigurable RISC-V Core for Approximate Computing

This is an HTML/Javascript CPU simulator and assembler for the CPU I designed. Originally, I created this CPU on paper many years ago for a homework assignment in college. More recently, I implemented my design in the Logisim logic simulator, and eventually it ran on an FPGA.

Verilog miniRV/RISC-V style CPU course project featuring single-cycle and five-stage pipeline designs with hazard handling.

A platform for learning and experimenting with logic circuits

Project implementations for the NAND2Tetris (Elements of Computing Systems) course, building a complete computer system from NAND gates to a functional CPU using HDL and low-level system design.

Computer Architecture UIUC SP 2018

Reusable 4-bit CPU in Logisim with Verilog HDL, ISA docs, and a browser playground

a simple risc processor

HyperSquid3: a near cycle-accurate Hitachi SH7709S (SH3) core

Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor

Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme

In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.

These are various files pertaining to a CPU I designed. Can be used in conjunction with my Logisim CPU youtube video series.

Graphics Processing Unit (GPU) Logisim component (JAR library). It can do blits, sprites, lines, polygons, and text faster than any other currently existing simulated Logisim GPU.

Aggreage of my past CPU designs.

MESAx8 - Minimal Extensible System Architecture x8

A Turing-complete 8-bit computer built entirely on breadboards using discrete logic chips

This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.

Sample Verilog codes for digital circuits