Awesome RISC-V

RISC-V is a popular architecture for microcontrollers and embedded systems.

Contents

• Open Source Implementations
  • Accelerators
  • Cores
  • SoCs
• Open Source Toolchains
  • Design Environment
  • HDLs
  • Simulators/Emulators
  • Verification and Testing Environment
• Hardware
  • Educational Boards
• Technical Resources
  • Articles
  • Books
  • Courses
  • Documentation
  • Papers and Publications
  • Tutorials
  • Videos
• Social Media
  • Forums
  • Google Groups
  • Reddit
  • Telegram

Open Source Implementations

Open source implementations of the RISC-V architecture.

Accelerators

• DANA - Dynamically Allocated Neural Network (DANA) Accelerator.

Cores

Open source RISC-V cores with proper documentation.

• bigPULP - Big version of the PULP platform with large cluster configurations for HPC workloads.
• biRISC-V - 32-bit dual-issue in-order RISC-V CPU.
• BOOM - Berkeley Out-of-Order RISC-V Processor.
• CDL Hardware - Hardware designs in Cycle Description Language (CDL) targeting RISC-V.
• CV32E40P - OpenHW Group CORE-V CV32E40P RISC-V IP.
• CVA6 - 6-stage, single-issue in-order RISC-V core maintained by the OpenHW Group.
• DarkRISCV - Experimental RISC-V implementation in Verilog, fitting in a small FPGA.
• E203 - Hummingbird E203 Opensource Processor Core.
• FlexPRET - 5-stage, fine-grained multithreaded RISC-V processor.
• Freedom - By SiFive for its Freedom E300 and U500 platforms.
• FWRISC - Featherweight RISC-V implementation.
• FWRISC-S - Extended variant of the FWRISC featherweight RISC-V core with added CSR support.
• Ibex - Small, 32-bit RISC-V core from lowRISC, formally verified and production-proven.
• KLESSYDRA-F03 - Interleaved multithreaded RISC-V processor (F03 variant) with DSP extensions.
• KLESSYDRA-T02 - Interleaved multithreaded RISC-V processor (T02 variant).
• KLESSYDRA-T03 - Interleaved multithreaded RISC-V processor (T03 variant).
• KLESSYDRA-T13 - Interleaved multithreaded RISC-V processor (T13 variant).
• Kronos - Lightweight, 3-stage in-order RV32I pipeline written in SystemVerilog.
• Leros - Tiny accumulator-based processor core targeting FPGAs.
• lipsi - Probably the smallest processor in the world, implemented in Chisel.
• Lizard - Modular, out-of-order RISC-V processor built with PyMTL.
• Maestro - RISC-V RV32I processor implemented in VHDL.
• Minerva - 32-bit RISC-V soft processor.
• MR1 - Minimal RISC-V RV32I core implemented in SpinalHDL.
• mriscv - 32-bit pipelined RISC-V processor implemented in Verilog.
• NEORV32 - Customizable, extensible MCU-class 32-bit soft-core CPU and SoC written in VHDL.
• NutShell - RISC-V processor developed by the University of Chinese Academy of Sciences.
• OpenPiton - World's first open source, general purpose, multithreaded manycore processor.
• patmos - Time-predictable VLIW processor.
• PicoRV32 - Size-Optimized RISC-V CPU.
• PULP - Parallel Ultra-Low-Power open-source multi-core computing platform.
• Rattlesnake - RISC-V RV32IMC Soft CPU, with a Security-Hardened Processor Core.
• Reindeer - PulseRain soft CPU supporting the RISC-V RV32IM instruction set.
• ReonV - RISC-V implementation based on a modified version of the Leon3 SPARC processor.
• RISCV-CLaSH - RiscV processor implementing the RV32I instruction set written in clash.
• riscv-mini - Simple three-stage RISC-V pipeline written in Chisel.
• Riscy - MIT CSAIL family of open-sourced, formally verified RISC-V processors.
• RiscyOO - MIT CSAIL out-of-order RISC-V processor with memory model support.
• Rocket - Parameterizable RISC-V SoC generator from UC Berkeley.
• RPU - Basic RISC-V CPU implementation in VHDL.
• RSD - Out-of-order superscalar RISC-V processor written in SystemVerilog.
• RV01 - Pipelined RV32I implementation on OpenCores targeting FPGAs.
• RV12 - Single-issue, in-order RV32I/RV64I RISC-V core from RoaLogic.
• Sail RISC-V - RISCV Sail Model.
• SCR1 - Free and open-source MCU-class RISC-V core from Syntacore.
• SERV - Award-winning ultra-compact bit-serial RISC-V core.
• Shakti C-Class - Application-class 64-bit RISC-V core from IIT Madras.
• Shakti E-Class - Embedded-class 32-bit RISC-V core from IIT Madras.
• Sodor - Educational collection of simple RISC-V processors written in Chisel by UC Berkeley.
• SSRV - SuperScalar-RISCV-CPU.
• Steel - Simple, 32-bit RISC-V processor core designed to be easily embedded into SoCs.
• SweRV - EH1 SweRV RISC-V CoreTM 1.8 from Western Digital.
• SweRV EH2 - EH2 SweRV RISC-V CoreTM 1.2 from Western Digital.
• SweRV EL2 - EL2 SweRV RISC-V CoreTM 1.2 from Western Digital.
• Taiga - 32-bit RISC-V processor designed for Xilinx FPGAs, targeting high performance.
• Tiny Risc-V - Easy-to-understand, from-scratch RISC-V implementation written in Verilog.
• VeeR EL2 - CHIPS Alliance VeeR EL2 RISC-V Core; the actively maintained successor to the Western Digital SweRV family.
• VexRiscv - FPGA-friendly 32-bit RISC-V implementation written in SpinalHDL.
• Wally (CVW) - CORE-V Wally: a configurable, 5-stage-pipeline RISC-V processor associated with the RISC-V System-on-Chip Design textbook by Harris et al.
• WARP-V - Open-source RISC-V core IP you can shape to your needs.
• XiangShan - Open-source high-performance out-of-order RISC-V processor developed at the Institute of Computing Technology, Chinese Academy of Sciences.
• RISCV-CPU - A 6-stage pipelined RV32IM core on FPGA, achieving 263.7 CoreMark and 91.0 DMIPS at 100 MHz.

SoCs

A curated list of RISC-V SoCs, available as open sources.

• Icicle - 32-bit RISC-V system on chip for iCE40 HX8K, iCE40 UP5K and ECP5 FPGAs.
• Iob-SoC - Template for building RISC-V-based SoCs using open-source tools.
• PicoSoC - Simple example SoC using PicoRV32.
• Raven - ASIC implementation of the PicoSoC PicoRV32.
• Riscy SoC - RISC-V SoC implementation targeting Xilinx FPGAs.
• Shakti SoC - Complete SoC built around the Shakti RISC-V processor family from IIT Madras.

Open Source Toolchains

Open source toolchains for designing and developing RISC-V systems.

Design Environment

• BRSIC-V - Browser-based RISC-V architecture design space exploration tool from Boston University.
• Chipyard - Framework for agile development of Chisel-based systems-on-chip.
• Firrtl - Flexible Internal Representation for RTL.
• FTPVL - FPGA Tool Performance Visualization Library.
• LowRISC Chip - lowRISC SoC platform built on the Rocket RISC-V core.
• nextpnr - Portable FPGA place and route tool.
• PULPino - Single-core microcontroller system, based on 32-bit RISC-V cores.
• PULPissimo - Microcontroller architecture of the more recent PULP chips.
• RISC-V GNU Toolchain - RISC-V GNU Compiler Toolchain.
• RISC-V Linux - Build Fedora Gnome Desktop on RISC-V.
• Treadle - Chisel/Firrtl Execution Engine.

HDLs

• CHISEL - Hardware Design Language that facilitates advanced circuit generation and design reuse in Scala.
• Chisel/FIRRTL Hardware Compiler Framework - Official website for the Chisel HDL and FIRRTL compiler framework.

Simulators/Emulators

Open source Emulators and Simulators for designing and testing RISC-V systems.

• Dromajo - Esperanto Technology's RISC-V Reference Model.
• FireSim - Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation.
• FireSim-NVDLA - Full-system simulator integrated with NVIDIA Deep Learning Accelerator (NVDLA).
• FuseSoC - Award-winning package manager and build tool set for HDL projects.
• GAP8 SDK - SDK for the GAP8 RISC-V multi-core IoT application processor by GreenWaves Technologies.
• gem5 - The gem5 computer-system architecture simulator; widely used in academia for RISC-V microarchitecture research.
• QEMU - The leading open-source machine emulator and virtualizer; supports both RV32 and RV64 system and user-mode emulation.
• RARS - RISC-V Assembler and Runtime Simulator.
• Renode - Antmicro's open-source simulation framework with excellent RISC-V support; ideal for embedded and multi-core prototyping.
• Ripes - Visual computer architecture simulator and assembly code editor.
• riscv-VM - OpenHW Group's RISC-V Virtual Machine.
• Shakti SDK - Software development kit for the Shakti RISC-V processor family from IIT Madras.
• Spike - RISC-V ISA Simulator.
• SweRV ISS - Instruction Set Simulator for the SweRV RISC-V core family.
• TinyEMU - System emulator for the RISC-V and x86 architectures.
• TLBSim - Fast TLB simulator for RISC-V systems.
• Venus - Browser-based RV32 assembler and runtime simulator used in UC Berkeley's CS 61C course; ideal for beginners.
• Verilator - Fastest Verilog/SystemVerilog simulator.
• WebRISC-V - Web-based graphical pipelined datapath simulation environment built for the RISC-V.

Verification and Testing Environment

• Axe - Automatic black box testing.
• BOOM Attacks - BOOM Speculative Attacks.
• CHISEL Tester - Testing utilities for circuits written in Chisel.
• RISC-V DV - SV/UVM based open-source instruction generator for RISC-V processor verification.
• RISC-V Formal - Open-source formal verification framework for RISC-V processors.
• RISC-V Tests - Unit tests for RISC-V processors.
• RISC-V Torture - Random torture test generator for RISC-V processors.
• UVM - Universal Verification Methodology (UVM) library for open-source EDA flows.

Hardware

Physical boards and platforms for hands-on RISC-V experimentation.

Educational Boards

Affordable and accessible RISC-V development boards recommended for students and researchers.

• HiFive1 Rev B - SiFive's Arduino-compatible RISC-V microcontroller board; an accessible entry point for bare-metal embedded programming.
• Milk-V Duo - Extremely low-cost ($5–$9) ultra-compact embedded Linux board based on a RISC-V + ARM dual-core SoC; great for IoT learning.

Technical Resources

Resources to help you make your own designs.

Articles

• 2019 : A year of RISC-V and Open source silicon - Year-in-review article covering the biggest RISC-V open-source silicon milestones of 2019.

• Embedded Linux on RISC-V - ELCE 2018 slides on bringing embedded Linux to RISC-V platforms.

• Learn with Shakti - Introductory learning resource for the Shakti RISC-V processor from IIT Madras.

• UC Berkeley RISC-V Work - Page on RISC-V-related work from UC Berkeley.

• RISC-V Bases and Extensions Explained - Accessible overview of the RISC-V base ISA and its standard extensions.

• RISC-V RV32I assembly with Ripes simulator - Tutorial on writing and visualizing RV32I assembly using the Ripes simulator.

• RISC-V Notes - Community-maintained collection of notes, links, and learning resources for RISC-V.

• RISC-V on Debian - Debian wiki page on RISC-V port status and build instructions.

• Sail - Page for the Sail ISA specification language used to formally describe RISC-V.

Books

• Digital Design with Chisel - Open-source textbook on hardware design using Chisel, with free PDF available.
• RISC-V Assembly Language Programming - Free, open-source textbook (with PDF releases) covering RV32I assembly from first principles; actively maintained by John Winans.
• RISC-V ISA Specification Manual - The official, open-source RISC-V Instruction Set Manual (Volumes I & II); the definitive reference for the unprivileged and privileged ISA.

Courses

• Building a RISC-V CPU Core (LFD111x) - Free Linux Foundation course on edX covering hands-on CPU microarchitecture design using open-source tools (TL-Verilog / Makerchip).
• Complex Digital Systems - By MIT.
• Computer Architecture, Summer 2017 - By Oakland University.
• Debugging & Verifying Programs - By University of Texas.
• Introduction to RISC-V (LFD110x) - Free Linux Foundation course on edX; covers the RISC-V ISA, specifications, and ecosystem; ideal starting point for students.
• Organization of Digital Computers Laboratory - By UC Irvine.

Documentation

• Chipyard Docs - Official documentation for the Chipyard SoC design framework.
• CHISEL Cheatsheet - Quick-reference cheatsheet for the Chisel hardware design language.
• Ripes Wiki - Official wiki and introduction for the Ripes RISC-V visual simulator.
• RISCV-FS - RISC-V formal ISA Specification.

Papers and Publications

• A Case for OS-Friendly Hardware Accelerators - Paper arguing for OS-managed hardware accelerator interfaces.

• A Hardware Accelerator for Tracing Garbage Collection - IEEE paper on custom hardware support for garbage collection in managed-runtime environments.

• A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications - IEEE paper on compact CNN acceleration for embedded vision.

• A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI - IEEE paper on integrated power-management for RISC-V vector processors.

• A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI - IEEE paper on energy-efficient RISC-V vector cores with integrated DC-DC converters.

• Accelerating Deep Convolutional Neural Networks Using Specialized Hardware - Microsoft Research whitepaper on dedicated CNN hardware acceleration.

• AI Requires Many Approaches - Linley Group whitepaper on diverse hardware strategies for AI inference.

• An Agile Approach to Building RISC-V Microprocessors - IEEE paper on agile hardware development methodology applied to RISC-V.

• Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI - ArXiv paper on the high-performance Ara vector unit for RISC-V.

• BOOM v2: an open-source out-of-order RISC-V core - UC Berkeley technical report on the second-generation BOOM processor.

• BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox - ArXiv paper describing the BRISC-V design-space exploration framework.

• Cambricon: An Instruction Set Architecture for Neural Networks - IEEE paper introducing an ISA tailored to neural network operations.

• Chipyard - An Integrated SoC Research and Implementation Environment - IEEE paper presenting the Chipyard SoC development framework.

• Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs - IEEE Micro article on agile SoC construction using Chipyard.

• Design and Implementation of CNN Custom Processor Based on RISC-V Architecture - IEEE paper on a RISC-V custom processor extension for CNN inference.

• Design of the RISC-V Instruction Set Architecture - Andrew Waterman's PhD dissertation on the design philosophy of the RISC-V ISA.

• DianNao: A Small-Footprint High-Throughput Accelerator for Ubiquitous Machine-Learning - ASPLOS 2014 paper on the influential DianNao neural network accelerator.

• FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design - ASPLOS 2020 paper on co-design profiling using FPGA simulation.

• FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud - ISCA 2018 paper introducing the FireSim FPGA simulation platform.

• FPGA-accelerated machine learning inference as a service for particle physics computing - ArXiv paper on using FPGAs for ML inference in particle physics pipelines.

• GAP-8: A RISC-V SoC for AI at the Edge of the IoT - IEEE paper on the GAP-8 multi-core RISC-V SoC for edge AI inference.

• Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures - Paper on the Gemmini systolic array generator integrated with the Rocket/BOOM RISC-V ecosystem.

• Hardware/Software Codesign for Mobile Speech Recognition - Interspeech 2013 paper on co-designed ASR acceleration for mobile devices.

• MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip - IEEE paper on a fully pipelined FPGA CNN accelerator with on-chip mapping.

• Minimizing Computation in Convolutional Neural Networks - Paper presenting techniques to reduce computation in CNN inference.

• Nested-Parallelism PageRank on RISC-V Vector Multi-Processors - CARRV 2019 paper on nested-parallel PageRank on the Hwacha RISC-V vector unit.

• OSEK-V: Application-Specific RTOS Instantiation in Hardware - LCTES 2017 paper on hardware-level RTOS instantiation for RISC-V.

• Out of order floating point coprocessor for RISC V ISA - IEEE paper on an out-of-order FPU coprocessor design for RISC-V.

• PHANTOM: Practical Oblivious Computation in a Secure Processor - CCS 2013 paper on the PHANTOM oblivious computation system in secure processors.

• Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI - IEEE paper on fine-grained power management for RISC-V vector workloads.

• PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors - ArXiv paper on quantized NN acceleration on the PULP RISC-V platform.

• RISC-V out-of-order data conversion co-processor - IEEE paper on a data-format conversion coprocessor for RISC-V pipelines.

• RV-CNN: Flexible and Efficient Instruction Set for CNNs Based on RISC-V Processors - Paper proposing a RISC-V ISA extension optimized for CNN workloads.

• Scratchpad memory: a design alternative for cache on-chip memory in embedded systems - IEEE paper comparing scratchpad and cache memory for embedded RISC-V SoCs.

• SHAKTI Processors: An Open-Source Hardware Initiative - IEEE paper introducing the Shakti family of open-source RISC-V processors from IIT Madras.

• SHAKTI-F: A Fault Tolerant Microprocessor Architecture - IEEE paper on fault-tolerant extensions to the Shakti RISC-V architecture.

• Simty: a Synthesizable General-Purpose SIMT Processor - Inria paper presenting the Simty SIMT processor built on RISC-V.

• Simty: generalized SIMT execution on RISC-V - Workshop paper on generalizing SIMT execution semantics for RISC-V.

• SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine - CARRV 2020 paper on the third-generation BOOM out-of-order RISC-V core.

• Specification for the FIRRTL Language - Formal specification of the FIRRTL intermediate representation used in Chisel-based design flows.

• The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor - UC Berkeley technical report introducing the first-generation BOOM processor.

• The Case for RISC-V in Space - Paper presenting RISC-V as a viable ISA for space-grade processor designs.

• The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA - Original UC Berkeley technical report defining the RISC-V base ISA.

• The Rocket Chip Generator - UC Berkeley technical report on the parameterizable Rocket Chip SoC generator.

• TIMBER-V: Tag-Isolated Memory Bringing Fine-grained Enclaves to RISC-V - NDSS 2019 paper on tag-based memory isolation for RISC-V secure enclaves.

• Towards a High-Performance RISC-V Emulator - Paper exploring micro-optimization techniques for RISC-V software emulation.

• Towards General-Purpose Neural Network Computing - IEEE paper on domain-specific neural network acceleration.

• Tuning Algorithms and Generators for Efficient Edge Inference - ArXiv paper on algorithm-level tuning for resource-efficient neural network inference.

• Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research - CARRV 2019 paper on using FireSim for end-to-end RISC-V research workflows.

Tutorials

• Advanced Examples of Using Chisel - Wiki page with advanced Chisel hardware design examples using the Sodor RISC-V cores.
• CHISEL Bootcamp - Interactive Jupyter-notebook-based bootcamp for learning Chisel hardware design.
• Cookbook - Community-contributed Chisel patterns and solutions wiki.
• How I built a RISC-V CPU Core in a span of 5 days - Workshop repository documenting a hands-on RISC-V TL-Verilog CPU build in five days.
• Intensivate's Learning Journey for Chisel - Community wiki documenting a structured learning path for Chisel hardware design.
• Notes for Rocket-Chip - Annotated reading notes on the Rocket Chip generator source code.

Videos

• Looking into Hello World on RISC-V by Dennis Clarke - Live stream walkthrough of a Hello World program running on RISC-V hardware.
• R32V2020 32-Bit RISC CPU Design - YouTube playlist on designing a custom 32-bit RISC CPU from scratch.
• RISC-V ASM Tutorial Collection - By Western Digital Corporation.
• RISC-V Workshop Zurich - Recordings from the RISC-V Workshop held in Zurich covering ISA development and ecosystem updates.

Social Media

These social media profiles will update about recent RISC-V related news.

Forums

• OSDForum - Open-source digital design forum covering RISC-V, FPGAs, and EDA topics.
• RISC-V official forum - Official RISC-V International technical forums for ISA and ecosystem discussions.

Google Groups

• Chisel Users - Community mailing list for users of the Chisel hardware design language.
• RISC-V HW Dev - Official RISC-V hardware development mailing list.
• RISC-V ISA Dev - Official mailing list for RISC-V ISA specification development discussions.
• RISC-V Teach - Mailing list for educators using RISC-V in courses and academic programs.

Reddit

• RISC-V - Subreddit for RISC-V news, projects, and community discussion.

Telegram

• RISC-V - Telegram group for real-time RISC-V community chat.

This list grows with the community. Whether you've found a new open-source core, a great course, or a tool that made your RISC-V workflow significantly better, your contribution is welcome here.

Please read the Contribution Guidelines before opening a pull request. We follow the sindresorhus/awesome standard: every entry must have a description, a live https:// link, and be actively maintained.

Found a dead link or an outdated resource? Open an issue on GitHub — that's a contribution too!