FIR Filter for High-Speed Decimation

A 32-tap high-speed FIR decimation filter implemented in Verilog RTL, designed primarily for FPGA-based digital signal processing applications requiring power-of-two decimation factors.

The design uses a highly parallel architecture to process all filter taps simultaneously, with a fast adder tree for accumulation. The implementation is synthesized and placed/routed using Xilinx Vivado targeting the Zynq-7020 FPGA.

Overview

In digital signal-processing systems, signals are often sampled at a higher rate than required for subsequent processing. Decimation reduces the sampling rate by retaining samples at a lower rate after appropriate low-pass filtering.

The FIR filter performs low-pass filtering before downsampling. This limits unwanted higher-frequency components and helps prevent aliasing, where higher-frequency components fold into the lower-frequency band after sampling-rate reduction.

This implementation is primarily designed for power-of-two decimation factors, such as:

D = 2, 4, 8, 16, ...

Power-of-two decimation allows simple counter-based decimation control and is particularly convenient for FPGA-based implementations.

Architecture

The FIR filter consists of:

• 32 filter taps
• 32-bit signed input samples
• 32-bit signed coefficients
• 32 parallel multipliers
• Adder tree for fast accumulation
• Configurable decimation factor
• 69-bit signed accumulated output
• Verilog RTL implementation

Datapath

Input Sample
     │
     ▼
32-Tap Delay Line
     │
     ▼
32 Parallel 32×32 Multipliers
     │
     ▼
      Adder Tree
     │
     ▼
  FIR Filter Output
     │
     ▼
Decimation Control
     │
     ▼
Decimated Output

The parallel multiplier architecture allows all 32 filter coefficients to be processed simultaneously. The adder tree reduces the accumulation depth and provides a faster alternative to a serial accumulation structure.

FPGA Implementation

The design was implemented using Xilinx Vivado for the Zynq-7020 (xc7z020clg484-1) FPGA.

Implementation Results

Metric	Result
Number of taps	32
Input width	32-bit
Coefficient width	32-bit
DSP48E1	128
LUTs	2,642
Registers	1,000
Slice LUT utilization	4.97%
Slice register utilization	0.94%
DSP utilization	58.18%
Timing-closed frequency	50 MHz
Clock period	20 ns
WNS	+0.113 ns
TNS	0 ns
Hold WNS	+0.074 ns

All user-specified timing constraints were met at the 20 ns clock period (50 MHz).

Application Example

For an input sampling rate of 44.1 kHz and a decimation factor of 8:

Input sampling rate  = 44.1 kHz
Decimation factor     = 8
Output sampling rate = 5.5125 kHz

The FIR low-pass filter is applied before downsampling to reduce the possibility of aliasing.

Design Characteristics

The current implementation prioritizes parallel processing and speed over minimum FPGA resource utilization.

The architecture therefore uses multiple DSP resources to perform the 32 FIR multiplications in parallel. This makes the design suitable as a reference RTL implementation and baseline architecture for FPGA-based multirate DSP systems.

Verification

The RTL was verified using a Verilog testbench with different decimation factors, including:

• D = 4
• D = 8

Ramp inputs and known filter coefficients were used to verify FIR accumulation and decimation behavior.

Tools and Technology

• Verilog HDL
• RTL Design
• Xilinx Vivado 2024.2
• Xilinx Zynq-7020
• DSP48E1
• RTL Simulation
• FPGA Synthesis
• Placement and Routing
• Static Timing Analysis

Keywords

FIR Filter, FIR Decimator, High-Speed FIR, FPGA, Verilog, RTL, Digital Signal Processing, DSP, Multirate DSP, Decimation, Power-of-Two Decimation, 32-Tap FIR, Parallel FIR, Adder Tree, DSP48E1, Zynq-7020, Xilinx Vivado, FPGA Signal Processing, Hardware Accelerator, Digital Filter, Low-Pass FIR, Anti-Aliasing Filter, Signal Processing