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Add support for sqdmulh in aarch64 #340

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Merged
mkannwischer merged 3 commits into from
Oct 14, 2025
Merged

Add support for sqdmulh in aarch64 #340

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b50c1c7
AArch64: add `sqdmulh`'s vector variant support for aarch64
willieyz Oct 8, 2025
807d500
Cortex-A55: add instruction `sqdmulh` support cortex_a55 micro model
willieyz Oct 9, 2025
058f776
Cortex-A72: add instruction `sqdmulh` support cortex_a72 micro model
willieyz Oct 13, 2025
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6 changes: 6 additions & 0 deletions slothy/targets/aarch64/aarch64_neon.py
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Original file line number Diff line number Diff line change
Expand Up @@ -3131,6 +3131,12 @@ def make(cls, src):
return obj


class vqdmulh_vector(Vqdmulh):
pattern = "sqdmulh <Vd>.<dt>, <Va>.<dt>, <Vb>.<dt>"
inputs = ["Va", "Vb"]
outputs = ["Vd"]


class vqdmulh_lane(Vqdmulh):
pattern = "sqdmulh <Vd>.<dt0>, <Va>.<dt0>, <Vb>.<dt1>[<index>]"
inputs = ["Va", "Vb"]
Expand Down
14 changes: 13 additions & 1 deletion slothy/targets/aarch64/cortex_a55.py
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Expand Up @@ -70,6 +70,7 @@
vqrdmulh,
vqrdmulh_lane,
vqdmulh_lane,
vqdmulh_vector,
vbic,
vbic_imm_shifted,
q_ldr1_stack,
Expand Down Expand Up @@ -249,6 +250,7 @@ def get_min_max_objective(slothy):
vqrdmulh,
vqrdmulh_lane,
vqdmulh_lane,
vqdmulh_vector,
Ldr_Q,
Str_Q,
q_ldr1_stack,
Expand Down Expand Up @@ -433,6 +435,7 @@ def get_min_max_objective(slothy):
vqrdmulh,
vqrdmulh_lane,
vqdmulh_lane,
vqdmulh_vector,
Vmull,
Vmlal,
umov_d,
Expand Down Expand Up @@ -507,7 +510,16 @@ def get_min_max_objective(slothy):
is_qform_form_of([vadd, vsub]): 3,
is_dform_form_of([vadd, vsub]): 2,
(trn1, trn2, ASimdCompare): 2,
(vmul, vmul_lane, vqrdmulh, vqrdmulh_lane, vqdmulh_lane, Vmull, Vmlal): 4,
(
vmul,
vmul_lane,
vqrdmulh,
vqrdmulh_lane,
vqdmulh_lane,
vqdmulh_vector,
Vmull,
Vmlal,
): 4,
(
vmla,
vmla_lane,
Expand Down
4 changes: 4 additions & 0 deletions slothy/targets/aarch64/cortex_a72_frontend.py
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Expand Up @@ -79,6 +79,7 @@
vqrdmulh,
vqrdmulh_lane,
vqdmulh_lane,
vqdmulh_vector,
trn1,
trn2,
ASimdCompare,
Expand Down Expand Up @@ -186,6 +187,7 @@ def get_min_max_objective(slothy):
vqrdmulh,
vqrdmulh_lane,
vqdmulh_lane,
vqdmulh_vector,
Vmlal,
Vmull,
): [ExecutionUnit.ASIMD0],
Expand Down Expand Up @@ -235,6 +237,7 @@ def get_min_max_objective(slothy):
vmls,
vmls_lane,
vqdmulh_lane,
vqdmulh_vector,
): 2,
AArch64Move: 1,
(Vmull, Vmlal): 1,
Expand Down Expand Up @@ -278,6 +281,7 @@ def get_min_max_objective(slothy):
vmla,
vmla_lane,
vqdmulh_lane,
vqdmulh_vector,
): 5,
(Vmull, Vmlal): 1,
AArch64NeonCount: 3,
Expand Down
3 changes: 3 additions & 0 deletions tests/naive/aarch64/instructions.s
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Expand Up @@ -151,4 +151,7 @@ add x2, x30, x3, LSL #39
add x2, x30, x3, lsl #39
add x2, x30, x3, ASR #39
add x2, x30, x3, asr #39

sqdmulh v5.4s, v1.4s, v23.4s

end: