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Add inline-asm build to CI, fix build #91

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Merged
merged 1 commit into from
Jan 8, 2022
Merged

Add inline-asm build to CI, fix build #91

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5 changes: 5 additions & 0 deletions .github/workflows/ci.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,11 @@ jobs:
run: cargo check --target x86_64-unknown-linux-gnu
- name: Run CI script for riscv32imac-unknown-none-elf under ${{ matrix.rust }}
run: cargo check --target riscv32imac-unknown-none-elf
- name: Run CI script for riscv32imac-unknown-none-elf (inline-asm) under ${{ matrix.rust }}
run: |
if [ "${{ matrix.rust }}" == "nightly" ]; then
cargo check --target riscv32imac-unknown-none-elf --features inline-asm
fi
- name: Run CI script for riscv64imac-unknown-none-elf under ${{ matrix.rust }}
run: cargo check --target riscv64imac-unknown-none-elf
- name: Run CI script for riscv64gc-unknown-none-elf under ${{ matrix.rust }}
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4 changes: 2 additions & 2 deletions src/asm.rs
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Expand Up @@ -7,7 +7,7 @@ macro_rules! instruction {
pub unsafe fn $fnname() {
match () {
#[cfg(all(riscv, feature = "inline-asm"))]
() => asm!($asm),
() => core::arch::asm!($asm),

#[cfg(all(riscv, not(feature = "inline-asm")))]
() => {
Expand Down Expand Up @@ -58,7 +58,7 @@ instruction!(
pub unsafe fn sfence_vma(asid: usize, addr: usize) {
match () {
#[cfg(all(riscv, feature = "inline-asm"))]
() => asm!("sfence.vma {0}, {1}", in(reg) addr, in(reg) asid),
() => core::arch::asm!("sfence.vma {0}, {1}", in(reg) addr, in(reg) asid),

#[cfg(all(riscv, not(feature = "inline-asm")))]
() => {
Expand Down
1 change: 1 addition & 0 deletions src/lib.rs
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Expand Up @@ -15,6 +15,7 @@

#![no_std]
#![cfg_attr(feature = "inline-asm", feature(asm))]
#![cfg_attr(feature = "inline-asm", feature(asm_const))]

extern crate bare_metal;
extern crate bit_field;
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12 changes: 6 additions & 6 deletions src/register/macros.rs
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Expand Up @@ -7,7 +7,7 @@ macro_rules! read_csr {
#[cfg(all(riscv, feature = "inline-asm"))]
() => {
let r: usize;
asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number);
core::arch::asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number);
r
}

Expand Down Expand Up @@ -36,7 +36,7 @@ macro_rules! read_csr_rv32 {
#[cfg(all(riscv32, feature = "inline-asm"))]
() => {
let r: usize;
asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number);
core::arch::asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number);
r
}

Expand Down Expand Up @@ -102,7 +102,7 @@ macro_rules! write_csr {
unsafe fn _write(bits: usize) {
match () {
#[cfg(all(riscv, feature = "inline-asm"))]
() => asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number),
() => core::arch::asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number),

#[cfg(all(riscv, not(feature = "inline-asm")))]
() => {
Expand All @@ -128,7 +128,7 @@ macro_rules! write_csr_rv32 {
unsafe fn _write(bits: usize) {
match () {
#[cfg(all(riscv32, feature = "inline-asm"))]
() => asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number),
() => core::arch::asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number),

#[cfg(all(riscv32, not(feature = "inline-asm")))]
() => {
Expand Down Expand Up @@ -178,7 +178,7 @@ macro_rules! set {
unsafe fn _set(bits: usize) {
match () {
#[cfg(all(riscv, feature = "inline-asm"))]
() => asm!("csrrs x0, {1}, {0}", in(reg) bits, const $csr_number),
() => core::arch::asm!("csrrs x0, {1}, {0}", in(reg) bits, const $csr_number),

#[cfg(all(riscv, not(feature = "inline-asm")))]
() => {
Expand All @@ -204,7 +204,7 @@ macro_rules! clear {
unsafe fn _clear(bits: usize) {
match () {
#[cfg(all(riscv, feature = "inline-asm"))]
() => asm!("csrrc x0, {1}, {0}", in(reg) bits, const $csr_number),
() => core::arch::asm!("csrrc x0, {1}, {0}", in(reg) bits, const $csr_number),

#[cfg(all(riscv, not(feature = "inline-asm")))]
() => {
Expand Down