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@davidharrishmc davidharrishmc commented Jun 11, 2024

Description

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Reference Model Used

  • SAIL
  • Spike
  • Other - < SPECIFY HERE >

Mandatory Checklist:

  • All tests are compliant with the test-format spec present in this repo ?
  • Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
  • Ran the new tests on RISCOF in coverage mode
  • Link to Google-Drive folder containing the new coverage reports (See this for more info): < SPECIFY HERE >
  • Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE >
  • Changelog entry created with a minor patch

Optional Checklist:

  • RISCV-V CTG PR link if tests were generated using it : < SPECIFY HERE >
  • Were the tests hand-written/modified ?
  • Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
  • If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

@davidharrishmc
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davidharrishmc commented Jun 11, 2024

Note that Sail does not yet support cbo.zero, so Sail throws an illegal instruction exception when attempting to simulate it during riscof compilation. Consequently I have been unable to fully test this. However, it should fix the problem Tim Hutt raised about the commit.

e3c5471#r143001732

davidharrishmc referenced this pull request Jun 11, 2024
…A fields in rv32e_m/B/src/ror-01 and rori-01 that listed I instead of E.
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@Timmmm Timmmm left a comment

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Thanks!

I have a PR to add cbo.zero support to Sail here if you want to test it:

riscv/sail-riscv#455

However I'd say it's not necessary for you to test it - I made the same changes locally and it selects the test now & passes. (I would have made a PR but you were faster than our PR approval process!)

Updated RVTEST_ISA string for RV64-cbo.zero test
@UmerShahidengr
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@jamesbeyond please have a look at it, this one is good to go, so you may merge this one

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@Timmmm Timmmm left a comment

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Thanks!

@allenjbaum
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allenjbaum commented Jun 12, 2024 via email

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LGTM

@jamesbeyond jamesbeyond merged commit 5973ec5 into riscv-non-isa:dev Jul 1, 2024
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5 participants