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treewide: Update CVA6 to pulp-v3, switch to HPDCache and pulp-linux #259

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4098faa
bender: update CVFPU dependency
ezelioli Jan 15, 2026
c3ab34d
bender: update CVA6 version
ezelioli Jan 15, 2026
c448533
cva6: Enable WB HPDCache
paulsc96 Jan 20, 2026
f3d8cb3
Bender: Fix CLIC by adding back CVA6 config
paulsc96 Feb 5, 2026
43a5df1
hw: Add an optional uncached DRAM alias
paulsc96 Feb 6, 2026
f038454
deps: Try out attempt to fix FIOM bug
paulsc96 Feb 14, 2026
c5e8cf5
target/xilinx: Clean up IP config
paulsc96 Feb 20, 2026
eb36f35
target/xilinx: Disable ECC on VCU128
paulsc96 Feb 20, 2026
8860eb0
WIP: Try additional options
paulsc96 Feb 20, 2026
ea77933
[WIP]: Try removing control interface as it should not be needed anymore
paulsc96 Feb 20, 2026
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6 changes: 3 additions & 3 deletions Bender.lock
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Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@ packages:
Git: https://github.com/pulp-platform/common_verification.git
dependencies: []
cva6:
revision: 4c02b24fe7c04690f626776a92274da24f80d1da
revision: 7ba0c723809721109e0f7dd377ffcf5d6cf31b49
version: null
source:
Git: https://github.com/pulp-platform/cva6.git
Expand All @@ -118,10 +118,10 @@ packages:
dependencies:
- axi
fpnew:
revision: e5aa6a01b5bbe1675c3aa8872e1203413ded83d1
revision: 58ca3c376beb914b2b80b811d4b270c063d4e6f7
version: null
source:
Git: https://github.com/pulp-platform/cvfpu.git
Git: https://github.com/openhwgroup/cvfpu.git
dependencies:
- common_cells
- fpu_div_sqrt_mvp
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2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -22,7 +22,7 @@ dependencies:
clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.38.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 }
cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v2.0.0 }
cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: paulsc/pulp-v3 }
iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.6.4 }
irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 }
opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 }
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2 changes: 1 addition & 1 deletion cheshire.mk
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Expand Up @@ -16,7 +16,7 @@ VLOG_ARGS ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps
VLOGAN_ARGS ?= -kdb -nc -assert svaext +v2k -timescale=1ns/1ps

# Common Bender flags for Cheshire RTL
CHS_BENDER_RTL_FLAGS ?= -t rtl -t cva6 -t cv64a6_imafdchsclic_sv39_wb
CHS_BENDER_RTL_FLAGS ?= -t rtl -t cva6 -t cv64a6_imafdchsclic_sv39_hpdcache_wb

# Define used paths (prefixed to avoid name conflicts)
CHS_ROOT ?= $(shell $(BENDER) path cheshire)
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20 changes: 17 additions & 3 deletions hw/cheshire_pkg.sv
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Expand Up @@ -157,6 +157,8 @@
bit LlcOutConnect;
doub_bt LlcOutRegionStart;
doub_bt LlcOutRegionEnd;
bit LlcEnableUncAlias;
doub_bt LlcOutUncStart;
// Parameters for VGA
byte_bt VgaRedWidth;
byte_bt VgaGreenWidth;
Expand Down Expand Up @@ -354,6 +356,11 @@
// own Xbar output with the specified region iff it is connected.
if (cfg.LlcOutConnect) begin i++; r++; ret.llc = i;
ret.map[r] = '{i, cfg.LlcOutRegionStart, cfg.LlcOutRegionEnd}; end
// Add an uncached alias of the LLC output if enabled.
// This bypasses all caches and can be used for uncached access to DRAM.
if (cfg.LlcEnableUncAlias) begin r++;
ret.map[r] = '{i, cfg.LlcOutUncStart, cfg.LlcOutUncStart +

Check warning on line 362 in hw/cheshire_pkg.sv

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/cheshire_pkg.sv#L362 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_pkg.sv" range:{start:{line:362 column:67}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:362 column:67} end:{line:363}} text:"        ret.map[r] = '{i, cfg.LlcOutUncStart, cfg.LlcOutUncStart +\n"}
cfg.LlcOutRegionEnd - cfg.LlcOutRegionStart}; end
// We can only internally map the SPM region if an LLC exists.
// Otherwise, we assume external ports map and back the SPM region.
// We map both the cached and uncached regions.
Expand Down Expand Up @@ -505,13 +512,18 @@
ret.NonIdempotentAddrBase = {64'h0000_0000, NoCieBase};
ret.NOCType = config_pkg::NOC_TYPE_AXI4_ATOP;
ret.NonIdempotentLength = {64'h1000_0000, 64'h6000_0000 - cfg.Cva6ExtCieLength};
ret.NrExecuteRegionRules = 6; // Debug, Bootrom, SPM, SPM Uncached, LLCOut, ExtCI;
ret.ExecuteRegionAddrBase = {AmDbg, AmBrom, AmSpm, AmSpmUnc, cfg.LlcOutRegionStart, CieBase};
ret.ExecuteRegionLength = {64'h40000, 64'h40000, SizeSpm, SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength};
ret.NrExecuteRegionRules = 6 + cfg.LlcEnableUncAlias; // (Uncached LLCOut), Debug, Bootrom, SPM, SPM Uncached, LLCOut, ExtCI;
ret.ExecuteRegionAddrBase [5:0] = {AmDbg, AmBrom, AmSpm, AmSpmUnc, cfg.LlcOutRegionStart, CieBase};
ret.ExecuteRegionLength [5:0] = {64'h40000, 64'h40000, SizeSpm, SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength};
if (cfg.LlcEnableUncAlias) begin
ret.ExecuteRegionAddrBase [6] = cfg.LlcOutUncStart;
ret.ExecuteRegionLength [6] = SizeLlcOut;
end
ret.NrCachedRegionRules = 3; // CachedSPM, LLCOut, ExtCI;
ret.CachedRegionAddrBase = {AmSpm, cfg.LlcOutRegionStart, CieBase};
ret.CachedRegionLength = {SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength};
ret.DebugEn = 1;
ret.RVH = 1;
ret.RVSCLIC = cfg.Clic;
ret.RVXHCLIC = cfg.ClicVsclic;
ret.CLICNumInterruptSrc = NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs;
Expand Down Expand Up @@ -607,6 +619,8 @@
LlcOutConnect : 1,
LlcOutRegionStart : 'h8000_0000,
LlcOutRegionEnd : 64'h1_0000_0000,
LlcEnableUncAlias : 1,
LlcOutUncStart : 64'h3_0000_0000, // Behind default Slink region
// VGA: RGB565
VgaRedWidth : 5,
VgaGreenWidth : 6,
Expand Down
35 changes: 13 additions & 22 deletions target/xilinx/scripts/impl_ip.tcl
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Expand Up @@ -36,11 +36,6 @@ switch $proj {
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \
CONFIG.CLKIN1_JITTER_PS {50.0} \
CONFIG.MMCM_CLKFBOUT_MULT_F {6.000} \
CONFIG.MMCM_CLKIN1_PERIOD {5.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {24} \
CONFIG.MMCM_CLKOUT2_DIVIDE {25} \
CONFIG.MMCM_CLKOUT3_DIVIDE {60} \
CONFIG.MMCM_CLKOUT4_DIVIDE {120} \
CONFIG.NUM_OUT_CLKS {4} \
CONFIG.CLKOUT1_JITTER {112.316} \
CONFIG.CLKOUT1_PHASE_ERROR {89.971} \
Expand Down Expand Up @@ -72,11 +67,6 @@ switch $proj {
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \
CONFIG.MMCM_CLKFBOUT_MULT_F {12.000} \
CONFIG.MMCM_CLKIN1_PERIOD {5.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {24} \
CONFIG.MMCM_CLKOUT2_DIVIDE {25} \
CONFIG.MMCM_CLKOUT3_DIVIDE {60} \
CONFIG.MMCM_CLKOUT4_DIVIDE {120} \
CONFIG.NUM_OUT_CLKS {4} \
CONFIG.CLKOUT1_JITTER {112.316} \
CONFIG.CLKOUT1_PHASE_ERROR {89.971} \
Expand Down Expand Up @@ -182,44 +172,45 @@ switch $proj {
switch $board {
vcu128 {
set_property -dict [list \
CONFIG.C0.DDR4_Clamshell {true} \
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \
CONFIG.System_Clock {No_Buffer} \
CONFIG.Reference_Clock {No_Buffer} \
CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \
CONFIG.C0.DDR4_InputClockPeriod {10000} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \
CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \
CONFIG.C0.DDR4_DataWidth {72} \
CONFIG.C0.DDR4_DataWidth {64} \
CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \
CONFIG.C0.DDR4_Ecc {true} \
CONFIG.C0.DDR4_AxiDataWidth {512} \
CONFIG.C0.DDR4_AxiAddressWidth {32} \
CONFIG.C0.DDR4_AxiIDWidth {8} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
CONFIG.C0.BANK_GROUP_WIDTH {1} \
CONFIG.C0.CS_WIDTH {2} \
CONFIG.C0.DDR4_AxiSelection {true} \
CONFIG.C0.DDR4_MCS_ECC {false} \
CONFIG.C0.DDR4_Ecc {false} \
CONFIG.C0.CS_WIDTH {2} \
CONFIG.C0.DDR4_Clamshell {true} \
] [get_ips $proj]
}
vcu118 {
set_property -dict [list \
CONFIG.System_Clock {No_Buffer} \
CONFIG.Reference_Clock {No_Buffer} \
CONFIG.C0.DDR4_MemoryPart {MT40A256M16LY-062E} \
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c1_062} \
CONFIG.C0.DDR4_InputClockPeriod {4000} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \
CONFIG.C0.DDR4_MemoryPart {MT40A256M16LY-062E} \
CONFIG.C0.DDR4_TimePeriod {833} \
CONFIG.C0.DDR4_DataWidth {64} \
CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \
CONFIG.C0.DDR4_MCS_ECC {false} \
CONFIG.C0.DDR4_CasWriteLatency {12} \
CONFIG.C0.DDR4_CasLatency {18} \
CONFIG.C0.DDR4_AxiDataWidth {512} \
CONFIG.C0.DDR4_AxiAddressWidth {31} \
CONFIG.C0.DDR4_AxiIDWidth {8} \
CONFIG.C0.BANK_GROUP_WIDTH {1} \
CONFIG.C0.DDR4_AxiSelection {true} \
CONFIG.C0.DDR4_MCS_ECC {false} \
CONFIG.C0.DDR4_Ecc {false} \
CONFIG.C0.DDR4_CasWriteLatency {12} \
CONFIG.C0.DDR4_CasLatency {18} \
CONFIG.C0.DDR4_TimePeriod {833} \
] [get_ips $proj]
}
default { nocfgexit $proj $board }
Expand Down
21 changes: 0 additions & 21 deletions target/xilinx/src/dram_wrapper_xilinx.sv
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Expand Up @@ -287,27 +287,6 @@ module dram_wrapper_xilinx #(
.c0_ddr4_s_axi_rresp ( cdc_dram_rsp.r.resp ),
.c0_ddr4_s_axi_rlast ( cdc_dram_rsp.r.last ),
.c0_ddr4_s_axi_rvalid ( cdc_dram_rsp.r_valid ),
`ifdef TARGET_VCU128
// TODO: Shouldn't we map this to an external reg port?
// AXI control
.c0_ddr4_s_axi_ctrl_awvalid ( '0 ),
.c0_ddr4_s_axi_ctrl_awready ( ),
.c0_ddr4_s_axi_ctrl_awaddr ( '0 ),
.c0_ddr4_s_axi_ctrl_wvalid ( '0 ),
.c0_ddr4_s_axi_ctrl_wready ( ),
.c0_ddr4_s_axi_ctrl_wdata ( '0 ),
.c0_ddr4_s_axi_ctrl_bvalid ( ),
.c0_ddr4_s_axi_ctrl_bready ( '0 ),
.c0_ddr4_s_axi_ctrl_bresp ( ),
.c0_ddr4_s_axi_ctrl_arvalid ( '0 ),
.c0_ddr4_s_axi_ctrl_arready ( ),
.c0_ddr4_s_axi_ctrl_araddr ( '0 ),
.c0_ddr4_s_axi_ctrl_rvalid ( ),
.c0_ddr4_s_axi_ctrl_rready ( '0 ),
.c0_ddr4_s_axi_ctrl_rdata ( ),
.c0_ddr4_s_axi_ctrl_rresp ( ),
.c0_ddr4_interrupt ( ),
`endif
// Others
.c0_init_calib_complete ( ),
.addn_ui_clkout1 ( dram_clk_o ),
Expand Down
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