pulp-platform · fischeti · Mar 4, 2026 · Mar 4, 2026 · Mar 4, 2026 · Mar 4, 2026
diff --git a/Bender.lock b/Bender.lock
@@ -197,14 +197,15 @@ packages:
     - common_cells
     - tech_cells_generic
   serial_link:
-    revision: 5a25f5a71074f1ebb6de7b5280f2b16924bcc666
-    version: 1.1.1
+    revision: e2ee103a9e5e852d73eb5c4bc838dd101ed04f53
+    version: null
     source:
       Git: https://github.com/pulp-platform/serial_link.git
     dependencies:
+    - apb
     - axi
+    - axi_stream
     - common_cells
-    - register_interface
   tech_cells_generic:
     revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
     version: 0.2.13

diff --git a/Bender.yml b/Bender.yml
@@ -12,6 +12,7 @@ package:
     - "Thomas Benz <tbenz@iis.ee.ethz.ch>"
 
 dependencies:
+  apb:                      { git: "https://github.com/pulp-platform/apb.git",                    version: 0.2.4  }
   apb_uart:                 { git: "https://github.com/pulp-platform/apb_uart.git",               version: 0.2.3  }
   axi:                      { git: "https://github.com/pulp-platform/axi.git",                    version: 0.39.8 }
   axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc.git",                version: 0.2.1  }
@@ -28,7 +29,7 @@ dependencies:
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }
   register_interface:       { git: "https://github.com/pulp-platform/register_interface.git",     version: 0.4.5  }
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.1  }
-  serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.1  }
+  serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            rev:     main   } # TODO: switch to versioned release
   unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.6  }
   dram_rtl_sim:             { git: "https://github.com/pulp-platform/dram_rtl_sim.git",           version: 0.1.1  }
 
@@ -39,8 +40,9 @@ sources:
   - hw/future/UsbOhciAxi4.v
   - hw/future/spinal_usb_ohci.sv
   - hw/bootrom/cheshire_bootrom.sv
-  - hw/regs/cheshire_reg_pkg.sv
-  - hw/regs/cheshire_reg_top.sv
+  - hw/regs/cheshire_regs_addrmap_pkg.sv
+  - hw/regs/cheshire_regs_pkg.sv
+  - hw/regs/cheshire_regs.sv
   - hw/cheshire_idma_wrap.sv
   - hw/cheshire_pkg.sv
   - hw/cheshire_soc.sv

diff --git a/cheshire.mk b/cheshire.mk
@@ -33,6 +33,9 @@ IDMA_ROOT         := $(shell $(BENDER) path idma)
 DRAM_RTL_SIM_ROOT := $(shell $(BENDER) path dram_rtl_sim)
 
 REGTOOL ?= $(CHS_REG_DIR)/vendor/lowrisc_opentitan/util/regtool.py
+PEAKRDL ?= peakrdl
+
+PEAKRDL_INCLUDES  := -I $(CHS_ROOT)/hw/regs
 
 ################
 # Dependencies #
@@ -83,8 +86,15 @@ include $(CHS_ROOT)/sw/sw.mk
 ###############
 
 # SoC registers
-$(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv: $(CHS_ROOT)/hw/regs/cheshire_regs.hjson
-	$(REGTOOL) -r $< --outdir $(dir $@)
+$(CHS_ROOT)/hw/regs/cheshire_regs_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_regs.sv: \
+    $(CHS_ROOT)/hw/regs/cheshire_regs.rdl
+	$(PEAKRDL) regblock $< -o $(CHS_ROOT)/hw/regs/ --cpuif apb4-flat --default-reset arst_n
+	@sed -i '1i// Copyright 2025 ETH Zurich and University of Bologna.\n// Solderpad Hardware License, Version 0.51, see LICENSE for details.\n// SPDX-License-Identifier: SHL-0.51\n' \
+	    $(CHS_ROOT)/hw/regs/cheshire_regs.sv $(CHS_ROOT)/hw/regs/cheshire_regs_pkg.sv
+
+$(CHS_ROOT)/hw/regs/cheshire_regs_addrmap_pkg.sv: $(CHS_ROOT)/hw/regs/cheshire_regs.rdl
+	$(PEAKRDL) raw-header $< --format svpkg -o $@
+	@sed -i '1i// Copyright 2025 ETH Zurich and University of Bologna.\n// Solderpad Hardware License, Version 0.51, see LICENSE for details.\n// SPDX-License-Identifier: SHL-0.51\n' $@
 
 # CLINT
 CLINTCORES ?= 1
@@ -110,20 +120,20 @@ $(AXI_VGA_ROOT)/.generated:
 	flock -x $@ $(MAKE) axi_vga && touch $@
 
 # Custom serial link
-$(CHS_SLINK_DIR)/.generated: $(CHS_ROOT)/hw/serial_link.hjson
-	cp $< $(dir $@)/src/regs/serial_link_single_channel.hjson
-	flock -x $@ $(MAKE) -C $(CHS_SLINK_DIR) update-regs BENDER="$(BENDER)" && touch $@
+SLINK_NUM_LANES ?= 4
+include $(CHS_SLINK_DIR)/slink.mk
 
 # iDMA
 include $(IDMA_ROOT)/idma.mk
 
 CHS_HW_ALL += $(IDMA_FULL_RTL)
-CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv
+CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_regs_addrmap_pkg.sv
+CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_regs_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_regs.sv
 CHS_HW_ALL += $(CLINTROOT)/.generated
 CHS_HW_ALL += $(OTPROOT)/.generated
 CHS_HW_ALL += $(AXIRTROOT)/.generated
 CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated
-CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated
+CHS_HW_ALL += $(CHS_SLINK_DIR)/src/regs/slink_reg.sv
 
 #####################
 # Generate Boot ROM #
@@ -147,11 +157,11 @@ CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/boo
 # Simulation #
 ##############
 
-$(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml
+$(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml $(CHS_ROOT)/Bender.lock
 	$(BENDER) script vsim -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOG_ARGS)" > $@
 	echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11" -cpppath "$(CXX_PATH)"' >> $@
 
-$(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh: $(CHS_ROOT)/Bender.yml
+$(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh: $(CHS_ROOT)/Bender.yml $(CHS_ROOT)/Bender.lock
 	$(BENDER) script vcs -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOGAN_ARGS)" --vlogan-bin="$(VLOGAN)" > $@
 	chmod +x $@
 

diff --git a/hw/bootrom/cheshire_bootrom.c b/hw/bootrom/cheshire_bootrom.c
@@ -24,13 +24,14 @@ int boot_passive(uint64_t core_freq) {
     // Initialize UART with debug settings
     uart_debug_init(&__base_uart, core_freq);
     // scratch[0] provides an entry point, scratch[1] a start signal
-    volatile uint32_t *scratch = reg32(&__base_regs, CHESHIRE_SCRATCH_0_REG_OFFSET);
+    volatile cheshire_regs_t *regs = CHS_REGS;
     // While we poll bit 2 of scratch[2], check for incoming UART debug requests
-    while (!(scratch[2] & 2))
+    while (!(regs->scratch[2].w & 2))
         if (uart_debug_check(&__base_uart)) return uart_debug_serve(&__base_uart);
     // No UART (or JTAG) requests came in, but scratch[2][2] was set --> run code at scratch[1:0]
-    scratch[2] = 0;
-    return boot_next_stage((void *)(uintptr_t)(((uint64_t)scratch[1] << 32) | scratch[0]));
+    regs->scratch[2].w = 0;
+    return boot_next_stage(
+        (void *)(uintptr_t)(((uint64_t)regs->scratch[1].w << 32) | regs->scratch[0].w));
 }
 
 int boot_spi_sdcard(uint64_t core_freq, uint64_t rtc_freq) {
@@ -69,8 +70,8 @@ int boot_i2c_24fc1025(uint64_t core_freq) {
 
 int main() {
     // Read boot mode and reference frequency
-    uint32_t bootmode = *reg32(&__base_regs, CHESHIRE_BOOT_MODE_REG_OFFSET);
-    uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET);
+    uint32_t bootmode = CHS_REGS->boot_mode.f.boot_mode;
+    uint32_t rtc_freq = CHS_REGS->rtc_freq.f.ref_freq;
     // Compute the boot core frequency using the reference clock
     uint64_t core_freq = clint_get_core_freq(rtc_freq, 2500);
     // In case of reentry, store return in scratch0 as is convention