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clint: systemRDL based register generation#252

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fischeti wants to merge 19 commits intomainfrom
fischeti/rdl-clint
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clint: systemRDL based register generation#252
fischeti wants to merge 19 commits intomainfrom
fischeti/rdl-clint

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@fischeti fischeti commented Nov 30, 2025

Integrates new clint version with systemRDL registers and an APB interface.

TODO:

  • Merge Convert registers to RDL, remove templating, convert to APB clint#5 and point clint to new release
  • Fix Gitlab CI: At the moment, the compilation fails because the installed peakrdl-regblock package is too old, which omits parameter definition in the generated packages.
  • Gitlab CI: fix ERROR: Cannot start server on port 3042: already in use. errors during FPGA boot jobs

@fischeti fischeti marked this pull request as ready for review November 30, 2025 17:30
@fischeti fischeti requested a review from paulsc96 December 1, 2025 09:13
@fischeti fischeti mentioned this pull request Dec 1, 2025
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paulsc96 commented Dec 2, 2025

I updated peakrdl-regblock and the build works in CI now.

I have no objections to this PR in principle. The question is if we want to coordinate this with other migrations to SystemRDL (and, with it, a migration from regbus to APB peripheral interconnect?) or merge it as is. The additional adapter is fine for a first approach, but I'd like to see a more principled integration in the next release.

Or, that's what I would say if the next release was my problem. But it is very likely not. So if you manage to identify a responsible maintainer for this repo, you can decide the next steps with them.

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fischeti commented Dec 4, 2025

Replacing the Regbus with an APB bus is definitely the end goal here.

I also don't like the converters too much, and migrating everything at once to SystemRDL would be nicer. However, I think this endeavour has a better chance of success when if it is approached step by step. First migrating all dependencies and then Cheshire itself, which would get rid of all the reg2apb converters again.

For me both ways would be fine. I will check with possible future maintainers first, as you said.

@fischeti fischeti requested a review from creinwar December 5, 2025 08:55
@fischeti fischeti force-pushed the fischeti/rdl-clint branch 2 times, most recently from f5dc500 to 739b0ba Compare January 16, 2026 08:23
@fischeti fischeti force-pushed the fischeti/rdl-clint branch from e8027aa to 91a5749 Compare March 4, 2026 13:46
@fischeti fischeti marked this pull request as draft March 4, 2026 13:47
@fischeti fischeti force-pushed the fischeti/rdl-clint branch 3 times, most recently from daf5625 to 9fc1536 Compare March 4, 2026 20:06
fischeti added 14 commits March 5, 2026 15:02
Replace the lowRISC regtool-based hjson register description with a
SystemRDL source and peakrdl-regblock generated RTL. The generated
register block uses an APB4-flat CPU interface; a reg_to_apb bridge is
added in cheshire_soc to convert from the internal reg_iface demux.

- Add hw/regs/rdl/cheshire_regs.rdl (register source)
- Generate hw/regs/rtl/cheshire_regs{,_pkg}.sv via peakrdl regblock
- Update cheshire.mk: PEAKRDL_INCLUDES, replace regtool make rule
- Update sw/sw.mk: switch cheshire.h to chs_sw_gen_hdr_rule_rdl
- Update Bender.yml: point to new rtl/ file locations
- Update hw/cheshire_soc.sv: add reg_to_apb bridge, new pkg types
- Delete hw/regs/cheshire_regs.hjson and hjson-generated SV files
…er access

Create hw/regs/cheshire.rdl as a top-level SystemRDL address map that places
cheshire_regs at its canonical base address (0x0300_0000, from cheshire_pkg.sv).

Update the build system to generate sw/include/regs/cheshire.h from this map
via `peakrdl c-header`, and fix the PEAKRDL_INCLUDES path. Update all SW files
(util.h, zsl.c, flash.c, gpt.c) to access registers through the generated
cheshire_regs_t struct instead of the old _REG_OFFSET macros.
… names

Replace all remaining uses of *_REG_OFFSET macros and CHESHIRE_HW_FEATURES_*_BIT
constants in SW tests with the struct-based cheshire_regs_t access pattern and
the corresponding CHESHIRE_REGS__HW_FEATURES__*_bp bit-position macros generated
by peakrdl c-header.
…er access

Add apb_mask bitmap to reg_out_t in cheshire_pkg.sv, where bit i indicates that
reg-bus port i requires an APB4-flat bridge. Populate it in gen_reg_out (currently
only cheshire_regs/RegOut.regs). In cheshire_soc.sv, replace the hand-wired
reg_to_apb instance and named APB signals with a generate loop that instantiates
reg_to_apb for every port flagged in apb_mask. Future APB IPs need only set their
bit in gen_reg_out — no structural changes to cheshire_soc.sv required.

Also fixes the previous use of undefined chs_regs_apb_req_t/resp_t types by
switching to apb_req_t/apb_resp_t already defined by CHESHIRE_TYPEDEF_ALL.
Add CHS_REGS macro to util.h for typed access to the Cheshire SoC register
file, replacing the previous chs_hw_feature_present() helper which required
ugly CHESHIRE_REGS__HW_FEATURES__*_bp bit-position macros. Hardware feature
checks now access named struct fields directly (e.g. CHS_REGS->hw_features.f.dma).

The base address is now derived from the RDL-generated cheshire_t struct via
offsetof(cheshire_t, cheshire_regs), removing the dependency on the linker
symbol __base_regs in C code. Remove the corresponding extern declaration
from params.h (the linker symbol is retained in common.ldh for smp.h assembly).

Update all call sites to use CHS_REGS consistently.
deps: Bump clint

deps: Bump clint

deps: Bump clint
@fischeti fischeti force-pushed the fischeti/rdl-clint branch from 9fc1536 to 62c6bfc Compare March 6, 2026 07:15
@fischeti fischeti force-pushed the fischeti/rdl-clint branch from 62c6bfc to eb9f817 Compare March 6, 2026 07:29
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