WIP: synthesis using yosys-slang

.gitignore

@@ -53,3 +53,7 @@ target/xilinx/build
 target/xilinx/out
 target/xilinx/scripts/add_sources.*
 vivado*
+
+# Bender/Yosys generated files
+target/yosys/out
+target/yosys/*.log

Bender.lock

@@ -17,17 +17,17 @@ packages:
     - obi_peripherals
     - register_interface
   axi:
-    revision: 78831b6feba265d5ee2683bbf42b4150f8a35c43
-    version: 0.39.8
+    revision: a256a3b86394fedf19e361047fccfdd7f6ef83e4
+    version: 0.39.9
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
     - common_cells
     - common_verification
     - tech_cells_generic
   axi_llc:
-    revision: 559bcbd09a5a884dbe31e2d72fd95d024e357f39
-    version: 0.2.1
+    revision: 59bb8a681347e1133f11a82190fbf4bc11900d9e
+    version: 0.2.2
     source:
       Git: https://github.com/pulp-platform/axi_llc.git
     dependencies:
@@ -62,8 +62,8 @@ packages:
     dependencies:
     - common_cells
   axi_vga:
-    revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084
-    version: 0.1.3
+    revision: 4d3e70d4f47bb74edc1ab68d99ffc02382e0fb9e
+    version: 0.1.4
     source:
       Git: https://github.com/pulp-platform/axi_vga.git
     dependencies:
@@ -95,8 +95,8 @@ packages:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
-    version: 0.2.3
+    revision: fb1885f48ea46164a10568aeff51884389f67ae3
+    version: 0.2.5
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
@@ -189,16 +189,16 @@ packages:
     - common_cells
     - common_verification
   riscv-dbg:
-    revision: 358f90110220adf7a083f8b65d157e836d706236
-    version: 0.8.1
+    revision: 2bc55e1e43a472b629a84ef3090a2aa13e13d351
+    version: 0.9.0
     source:
       Git: https://github.com/pulp-platform/riscv-dbg.git
     dependencies:
     - common_cells
     - tech_cells_generic
   serial_link:
-    revision: 5a25f5a71074f1ebb6de7b5280f2b16924bcc666
-    version: 1.1.1
+    revision: c55df03a1da06b00e567cf968b1b1a5f40c9f802
+    version: 1.1.2
     source:
       Git: https://github.com/pulp-platform/serial_link.git
     dependencies:
@@ -213,8 +213,8 @@ packages:
     dependencies:
     - common_verification
   unbent:
-    revision: e9c9d5cfb635f2d4668c816ce9235798cfecb297
-    version: 0.1.6
+    revision: af0c25ba9eaaefade8688a4a47ced999d4c5255d
+    version: null
     source:
       Git: https://github.com/pulp-platform/unbent.git
     dependencies:

Bender.yml

@@ -13,8 +13,8 @@ package:
 
 dependencies:
   apb_uart:                 { git: "https://github.com/pulp-platform/apb_uart.git",               version: 0.2.3  }
-  axi:                      { git: "https://github.com/pulp-platform/axi.git",                    version: 0.39.8 }
-  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc.git",                version: 0.2.1  }
+  axi:                      { git: "https://github.com/pulp-platform/axi.git",                    version: 0.39.9 }
+  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc.git",                version: 0.2.2  }
   axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      version: 0.8.2  }
   axi_rt:                   { git: "https://github.com/pulp-platform/axi_rt.git",                 version: 0.0.0-alpha.10 }
   axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                version: 0.1.3  }
@@ -27,9 +27,9 @@ dependencies:
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             version: 0.0.1-beta.1 }
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }
   register_interface:       { git: "https://github.com/pulp-platform/register_interface.git",     version: 0.4.5  }
-  riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.1  }
-  serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.1  }
-  unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.6  }
+  riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.9.0  }
+  serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.2  }
+  unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 rev: af0c25ba9eaaefade8688a4a47ced999d4c5255d  }
   dram_rtl_sim:             { git: "https://github.com/pulp-platform/dram_rtl_sim.git",           version: 0.1.1  }
 
 export_include_dirs:
@@ -62,3 +62,9 @@ sources:
       - target/xilinx/src/regs/chs_xilinx_reg_pkg.sv
       - target/xilinx/src/regs/chs_xilinx_reg_top.sv
       - target/xilinx/src/cheshire_top_xilinx.sv
+
+  - target: chs_synthesis
+    files:
+      - target/yosys/tc_sram_blackbox.sv
+      - target/yosys/tc_clk_blackbox.sv
+      - hw/cheshire_synth_wrapper.sv

docker-compose.yml

@@ -0,0 +1,21 @@
+# Copyright (c) 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Authors:
+# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
+
+services:
+  oseda:
+    image: hpretl/iic-osic-tools:2025.01
+    environment:
+      - UID=${UID}
+      - GID=${GID}
+    user: "${UID}:${GID}"
+    volumes:
+      - ./:/fosic/designs/cheshire
+    stdin_open: true
+    tty: true
+    working_dir: /fosic/designs/cheshire
+    entrypoint: /dockerstartup/scripts/ui_startup.sh
+    command: --skip bash

hw/cheshire_idma_wrap.sv

@@ -140,6 +140,7 @@ module cheshire_idma_wrap #(
     .axi_rsp_o  ( axi_slv_rsp_o ),
     .reg_req_o  ( dma_reg_req ),
     .reg_rsp_i  ( dma_reg_rsp ),
+    .reg_id_o   ( ),
     .busy_o     ( )
    );
 

hw/cheshire_synth_wrapper.sv

@@ -0,0 +1,136 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Authors:
+// Philippe Sauter <phsauter@iis.ee.ethz.ch>
+
+package cheshire_synth_wrapper_pkg;
+  `include "cheshire/typedef.svh"
+
+  import cheshire_pkg::*;
+
+  // generate the cheshire configuration used here
+  function automatic cheshire_cfg_t gen_cheshire_cfg();
+    cheshire_cfg_t ret = DefaultCfg;
+    // here you would modify the struct to change your configuration
+    ret.AxiUserWidth = 8; // avoid error: cannot select range of 8 elements from 'logic[1:0]'
+    return ret;
+  endfunction
+  localparam cheshire_cfg_t Cfg = gen_cheshire_cfg();
+
+  `CHESHIRE_TYPEDEF_ALL(, Cfg)
+endpackage
+
+
+module cheshire_synth_wrapper import cheshire_synth_wrapper_pkg::*; import cheshire_pkg::*; #(
+  parameter type axi_ext_llc_req_t  = axi_llc_req_t,
+  parameter type axi_ext_llc_rsp_t  = axi_llc_rsp_t,
+  parameter type axi_ext_mst_req_t  = axi_mst_req_t,
+  parameter type axi_ext_mst_rsp_t  = axi_mst_rsp_t,
+  parameter type axi_ext_slv_req_t  = axi_slv_req_t,
+  parameter type axi_ext_slv_rsp_t  = axi_slv_rsp_t,
+  parameter type reg_ext_req_t      = reg_req_t,
+  parameter type reg_ext_rsp_t      = reg_rsp_t
+) (
+  input  logic        clk_i,
+  input  logic        rst_ni,
+  input  logic        test_mode_i,
+  input  logic [1:0]  boot_mode_i,
+  input  logic        rtc_i,
+  // JTAG interface
+  input  logic  jtag_tck_i,
+  input  logic  jtag_trst_ni,
+  input  logic  jtag_tms_i,
+  input  logic  jtag_tdi_i,
+  output logic  jtag_tdo_o,
+  output logic  jtag_tdo_oe_o,
+  // UART interface
+  output logic  uart_tx_o,
+  input  logic  uart_rx_i,
+  // UART modem flow control
+  output logic  uart_rts_no,
+  output logic  uart_dtr_no,
+  input  logic  uart_cts_ni,
+  input  logic  uart_dsr_ni,
+  input  logic  uart_dcd_ni,
+  input  logic  uart_rin_ni,
+  // I2C interface
+  output logic  i2c_sda_o,
+  input  logic  i2c_sda_i,
+  output logic  i2c_sda_en_o,
+  output logic  i2c_scl_o,
+  input  logic  i2c_scl_i,
+  output logic  i2c_scl_en_o,
+  // GPIO interface
+  input  logic [31:0] gpio_i,
+  output logic [31:0] gpio_o,
+  output logic [31:0] gpio_en_o,
+  // SPI host interface
+  output logic                  spih_sck_o,
+  output logic                  spih_sck_en_o,
+  output logic [SpihNumCs-1:0]  spih_csb_o,
+  output logic [SpihNumCs-1:0]  spih_csb_en_o,
+  output logic [ 3:0]           spih_sd_o,
+  output logic [ 3:0]           spih_sd_en_o,
+  input  logic [ 3:0]           spih_sd_i,
+  // USB interface
+  input  logic                   usb_clk_i,
+  input  logic                   usb_rst_ni,
+  input  logic [UsbNumPorts-1:0] usb_dm_i,
+  output logic [UsbNumPorts-1:0] usb_dm_o,
+  output logic [UsbNumPorts-1:0] usb_dm_oe_o,
+  input  logic [UsbNumPorts-1:0] usb_dp_i,
+  output logic [UsbNumPorts-1:0] usb_dp_o,
+  output logic [UsbNumPorts-1:0] usb_dp_oe_o,
+  // VGA interface
+  output logic                         vga_hsync_o,
+  output logic                         vga_vsync_o,
+  output logic [Cfg.VgaRedWidth  -1:0] vga_red_o,
+  output logic [Cfg.VgaGreenWidth-1:0] vga_green_o,
+  output logic [Cfg.VgaBlueWidth -1:0] vga_blue_o,
+  // Serial link interface
+  input  logic [SlinkNumChan-1:0]                    slink_rcv_clk_i,
+  output logic [SlinkNumChan-1:0]                    slink_rcv_clk_o,
+  input  logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i,
+  output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o,
+  // External AXI LLC (DRAM) port
+  output axi_ext_llc_req_t axi_llc_mst_req_o,
+  input  axi_ext_llc_rsp_t axi_llc_mst_rsp_i,
+  // External AXI crossbar ports
+  input  axi_ext_mst_req_t [iomsb(Cfg.AxiExtNumMst):0] axi_ext_mst_req_i,
+  output axi_ext_mst_rsp_t [iomsb(Cfg.AxiExtNumMst):0] axi_ext_mst_rsp_o,
+  output axi_ext_slv_req_t [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_req_o,
+  input  axi_ext_slv_rsp_t [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_rsp_i,
+  // External reg demux slaves
+  output reg_ext_req_t [iomsb(Cfg.RegExtNumSlv):0] reg_ext_slv_req_o,
+  input  reg_ext_rsp_t [iomsb(Cfg.RegExtNumSlv):0] reg_ext_slv_rsp_i,
+  // Interrupts from and to external targets
+  input  logic [iomsb(Cfg.NumExtInIntrs):0]                                  intr_ext_i,
+  output logic [iomsb(Cfg.NumExtOutIntrTgts):0][iomsb(Cfg.NumExtOutIntrs):0] intr_ext_o,
+  // Interrupt requests to external harts
+  output logic [iomsb(NumIrqCtxts*Cfg.NumExtIrqHarts):0] xeip_ext_o,
+  output logic [iomsb(Cfg.NumExtIrqHarts):0]             mtip_ext_o,
+  output logic [iomsb(Cfg.NumExtIrqHarts):0]             msip_ext_o,
+  // Debug interface to external harts
+  output logic                               dbg_active_o,
+  output logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_req_o,
+  input  logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_unavail_i
+);
+
+  cheshire_soc #(
+    .Cfg                ( Cfg ),
+    .ExtHartinfo        ( '0 ),
+    .axi_ext_llc_req_t  ( axi_llc_req_t ),
+    .axi_ext_llc_rsp_t  ( axi_llc_rsp_t ),
+    .axi_ext_mst_req_t  ( axi_mst_req_t ),
+    .axi_ext_mst_rsp_t  ( axi_mst_rsp_t ),
+    .axi_ext_slv_req_t  ( axi_slv_req_t ),
+    .axi_ext_slv_rsp_t  ( axi_slv_rsp_t ),
+    .reg_ext_req_t      ( reg_req_t ),
+    .reg_ext_rsp_t      ( reg_rsp_t )
+  ) i_cheshire_soc (
+    .*
+  );
+
+endmodule

start_linux.sh

@@ -0,0 +1,16 @@
+#!/bin/sh
+# Copyright (c) 2025 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Authors:
+# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
+
+export UID=$(id -u)
+export GID=$(id -g)
+
+docker compose pull
+docker compose run \
+  -e PS1="\[\033[01;32m\]oseda: \[\033[00m\]\[\033[01;34m\]\w\[\033[00m\] $" \
+  -v /tmp/.X11-unix:/tmp/.X11-unix \
+  oseda

target/yosys/synthesis.sh

@@ -0,0 +1,22 @@
+#!/bin/bash
+# Copyright (c) 2025 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Authors:
+# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
+
+SCRIPTDIR="$(realpath $(dirname "${BASH_SOURCE[0]}"))"
+
+BENDER=${BENDER:-bender}
+YOSYS=${YOSYS:-yosys}
+
+CHS_BENDER_RTL_FLAGS=${CHS_BENDER_RTL_FLAGS:--t rtl -t cva6 -t cv64a6_imafdchsclic_sv39}
+BENDER_TARGETS="-t chs_synthesis -t asic $CHS_BENDER_RTL_FLAGS"
+BENDER_DEFINES="-D SYNTHESIS -D COMMON_CELLS_ASSERTS_OFF"
+
+cd $SCRIPTDIR
+mkdir -p out
+$BENDER script flist-plus $BENDER_TARGETS $BENDER_DEFINES > out/cheshire.f
+
+$YOSYS -q -l synthesis.log -s yosys.ys