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    57 repositories

    • OpenFPGA

      Public
      An Open-source FPGA IP Generator
      fpgafpga-soc
      fpgafpga-soc
      Verilog
      •
      MIT License
      •203•1.1k•136•14•Updated Aug 1, 2026Aug 1, 2026

    • LSOracle

      Public
      IDEA project source files
      logic-synthesis
      logic-synthesis
      Verilog
      •
      MIT License
      •41•115•21•4•Updated Apr 15, 2026Apr 15, 2026

    • FPGA_Secured_Bitstream

      Public
      eFGPA IP to decode on-the-fly an encrypted bitstream for different configuration protocol
      Verilog
      •
      MIT License
      •3•8•0•2•Updated Jan 10, 2026Jan 10, 2026

    • OpenROAD

      Public
      OpenROAD's unified application implementing an RTL-to-GDS Flow
      Verilog
      •
      BSD 3-Clause "New" or "Revised" License
      •971•2•0•0•Updated Oct 31, 2025Oct 31, 2025

    • ECE_5710_6710_F24

      Public
      University of Utah ECE 6710/5710 Lab Material
      Verilog
      •0•3•0•0•Updated Sep 15, 2025Sep 15, 2025

    • ECE_6710_5710_Project_Template

      Public
      Verilog
      •0•0•0•0•Updated Sep 9, 2025Sep 9, 2025

    • embedded-systems-template

      Public
      C
      •2•1•0•0•Updated Jan 29, 2025Jan 29, 2025

    • ChemAirU

      Public
      The University of Utah Research. This this a research project that will work on developing ChemAirU, a low-cost modular platform capable of detecting and monito…
      HTML
      •0•0•0•0•Updated Dec 13, 2024Dec 13, 2024

    • testchip_4t1r

      Public
      RRAM testchip designed to evaluate 4t1r configuration. Official submission repository for google MPW4 tapeout program.
      Verilog
      •
      MIT License
      •2•2•0•0•Updated Jan 11, 2024Jan 11, 2024

    • ASOracle

      Public
      Racket
      •
      MIT License
      •0•1•0•0•Updated Oct 4, 2023Oct 4, 2023

    • FPGA_Benchmark_Suite

      Public
      Modern industrial benchmark suite to evaluate FPGA architecture performance, tool performance, and enable FPGA architecture exploration.
      MIT License
      •0•2•0•0•Updated Aug 3, 2023Aug 3, 2023

    • OpenFPGA_tutorials

      Public
      MIT License
      •1•2•0•0•Updated Jul 11, 2023Jul 11, 2023

    • GF12_template

      Public
      Verilog
      •1•1•0•0•Updated Apr 5, 2023Apr 5, 2023

    • ChemAirUFPGA

      Public
      The code for the FPGA on the chem AirU
      VHDL
      •0•0•0•0•Updated Mar 30, 2023Mar 30, 2023

    • SOFA

      Public
      SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
      Verilog
      •
      MIT License
      •28•154•14•1•Updated Mar 17, 2023Mar 17, 2023

    • LSOracle-Plugin-packaging

      Public
      0•0•0•0•Updated Dec 31, 2022Dec 31, 2022

    • Caravel-SOFA-CHD

      Public
      Verilog
      •
      Apache License 2.0
      •0•4•0•0•Updated Dec 31, 2022Dec 31, 2022

    • Caravel-QLSOFA-HD

      Public
      Verilog
      •
      Apache License 2.0
      •1•2•0•0•Updated Dec 31, 2022Dec 31, 2022

    • Caravel-SOFA-HD

      Public
      Verilog
      •
      Apache License 2.0
      •139•2•0•0•Updated Dec 31, 2022Dec 31, 2022

    • ML-Mapper

      Public
      C
      •2•14•2•0•Updated Dec 31, 2022Dec 31, 2022

    • Caravel-QLAP3

      Public
      Verilog
      •
      Apache License 2.0
      •0•4•0•0•Updated Dec 31, 2022Dec 31, 2022

    • JPEG_LS

      Public
      Verilog
      •
      MIT License
      •7•25•1•0•Updated Dec 31, 2022Dec 31, 2022

    • rn-air-monitor

      Public
      JavaScript
      •2•0•0•1•Updated Dec 31, 2022Dec 31, 2022

    • airu-v2-wearable

      Public
      Wearable version of AirU version 2
      C
      •3•0•0•0•Updated Dec 31, 2022Dec 31, 2022

    • vtr-verilog-to-routing

      Public
      Verilog to Routing -- Open Source CAD Flow for FPGA Research
      C
      •
      Other
      •445•1•0•0•Updated Dec 31, 2022Dec 31, 2022

    • WeatherStation

      Public
      Personal Bluetooth Weather Station utilizing the ESP32 MCU
      Swift
      •1•0•1•0•Updated Dec 31, 2022Dec 31, 2022

    • CMOS_RRAM_Addon

      Public
      A design kit add-on for hybrid CMOS-RRAM full-custom exploration. This add-on can be used with any commercial CMOS design kits.
      HCL
      •
      GNU Lesser General Public License v3.0
      •5•5•0•0•Updated Dec 31, 2022Dec 31, 2022

    • MPack

      Public
      A packing tool to handle matrix-based FPGAs (MClusters) organization.
      C
      •
      GNU Lesser General Public License v3.0
      •2•1•0•0•Updated Dec 30, 2022Dec 30, 2022

    • MemoryCharacterizationSystem

      Public
      An FPGA-based low-cost RRAM test system.
      HTML
      •
      GNU Lesser General Public License v3.0
      •2•4•0•0•Updated Dec 30, 2022Dec 30, 2022

    • TIGFET-BCB

      Public
      A system-level evaluation of TIGFETs using the BCB3.0 methodology from Intel.
      MATLAB
      •1•1•0•0•Updated Dec 21, 2022Dec 21, 2022
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