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Clock network implementation notes

Status: Open.

#2658 In lnis-uofu/OpenFPGA;

· ganeshgore opened on Jul 24, 2026

[WIP] Regression test infrastructure refactoring

Status: Open.

#2649 In lnis-uofu/OpenFPGA;

· tangxifan opened on Jul 17, 2026

Support .gz for netlist generation commands

Status: Open.

#2648 In lnis-uofu/OpenFPGA;

· tangxifan opened on Jul 17, 2026

Clock network task fails without compress routing

Status: Open.

#2620 In lnis-uofu/OpenFPGA;

· ganeshgore opened on Jul 3, 2026

Consider adding explicit annotation for BUS based mux config bits

Status: Open.

#2619 In lnis-uofu/OpenFPGA;

· ganeshgore opened on Jul 1, 2026

VPR Analytical Placer Flow failed in a few testcases while classical flow succeed

Status: Open.

#2599 In lnis-uofu/OpenFPGA;

· tangxifan opened on Jun 21, 2026

[WIP] Potential conflicts between option 'sort_gsb_chan_node_in_edges' and 'reorder_incoming_edges' for command 'link_arch'

Status: Open.

#2431 In lnis-uofu/OpenFPGA;

· tangxifan opened on Mar 27, 2026

How to expand size?

Status: Open.

#2417 In lnis-uofu/OpenFPGA;

· moonbox6615 opened on Mar 10, 2026

Tile reference file includes logical dimension of tiles

Status: Open.

#2412 In lnis-uofu/OpenFPGA;

· tangxifan opened on Mar 5, 2026

Simulation Failure in 4-bit Multiplier Circuit

Status: Open.

#2335 In lnis-uofu/OpenFPGA;

· shimoshida opened on Jan 26, 2026

Undriven pins and unused inputs in sb_0__0_ routing module

Status: Open.

#2313 In lnis-uofu/OpenFPGA;

· AhmadHouraniah opened on Jan 13, 2026

N2_lut5 mode bitstream generation error when LUT6 is split into two LUT5s

Status: Open.

#2210 In lnis-uofu/OpenFPGA;

· Nakiana opened on Oct 26, 2025