Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add an OpenTitan custom "unimplemented device" with support for Comportable registers #146

Merged
merged 15 commits into from
Feb 13, 2025
+624 −160
Merged

Add an OpenTitan custom "unimplemented device" with support for Comportable registers #146

Changes from 1 commit
Commits
Show all changes
15 commits
Select commit Hold shift + click to select a range
12a7248
[ot] hw/opentitan: ot_unimp: create a custom unimplemented device for OT
rivos-eblot Feb 12, 2025
157cff8
[ot] hw/opentitan: ot_unimp: add comportable register management
rivos-eblot Feb 12, 2025
71a151f
[ot] hw/opentitan: ot_unimp: add traces for IRQ and Alerts
rivos-eblot Feb 12, 2025
5ce4121
[ot] hw/opentitan: ot_aes: fix invalid alert management
rivos-eblot Feb 12, 2025
420d205
[ot] hw/opentitan: ot_edn: fix missing alert test update
rivos-eblot Feb 12, 2025
5d2ad69
[ot] hw/opentitan: ot_plic_ext: fix memory map
rivos-eblot Feb 13, 2025
2b306e1
[ot] hw/riscv: ot_darjeeling: add missing UNIMP dependency
rivos-eblot Feb 12, 2025
54a6bcd
[ot] hw/riscv: ot_earlgrey: replace default unimplemented device with…
rivos-eblot Feb 12, 2025
3920c27
[ot] hw/riscv: ot_earlgrey: fix PLIC extension address
rivos-eblot Feb 12, 2025
95b70e0
[ot] hw/riscv: ot_earlgrey: configure IRQ and Alerts for unimplemente…
rivos-eblot Feb 12, 2025
456dfec
[ot] hw/riscv: ot_earlgrey: connect alerts of unimplemented devices
rivos-eblot Feb 12, 2025
022bdc2
[ot] hw/opentitan: ot_edn: fix coding style with clang-format
rivos-eblot Feb 13, 2025
f7c7cc8
[ot] hw/opentitan: all: remove default ot_id string creation.
rivos-eblot Feb 13, 2025
06c44d0
[ot] hw/riscv: ot_earlgrey: assign default ot_id name
rivos-eblot Feb 13, 2025
bc4d7b8
[ot] hw/riscv: ot_darjeeling: assign default ot_id name
rivos-eblot Feb 13, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Next Next commit
[ot] hw/opentitan: ot_edn: fix coding style with clang-format 
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
@rivos-eblot
rivos-eblot committed Feb 13, 2025
commit 022bdc285ae2874fff68232d135f408304a6089b
35 changes: 22 additions & 13 deletions hw/opentitan/ot_otp_eg.c
View file
Original file line number Diff line number Diff line change
@@ -308,8 +308,10 @@ REG32(LC_STATE, 2008u)

#define INTR_MASK (INTR_OTP_OPERATION_DONE_MASK | INTR_OTP_ERROR_MASK)
#define ALERT_TEST_MASK \
(R_ALERT_TEST_FATAL_MACRO_ERROR_MASK | R_ALERT_TEST_FATAL_CHECK_ERROR_MASK | \
R_ALERT_TEST_FATAL_BUS_INTEG_ERROR_MASK | R_ALERT_TEST_FATAL_PRIM_OTP_ALERT_MASK | \
(R_ALERT_TEST_FATAL_MACRO_ERROR_MASK | \
R_ALERT_TEST_FATAL_CHECK_ERROR_MASK | \
R_ALERT_TEST_FATAL_BUS_INTEG_ERROR_MASK | \
R_ALERT_TEST_FATAL_PRIM_OTP_ALERT_MASK | \
R_ALERT_TEST_RECOV_PRIM_OTP_ALERT_MASK)

#define SW_CFG_WINDOW 0x800u
@@ -667,14 +669,13 @@ static bool ot_otp_eg_is_readable(OtOTPEgState *s, int partition, unsigned addr)
READ_LOCK);
break;
case OTP_PART_ROT_CREATOR_AUTH_CODESIGN:
rdaccess =
(bool)SHARED_FIELD_EX32(s->regs[R_ROT_CREATOR_AUTH_CODESIGN_READ_LOCK],
READ_LOCK);
rdaccess = (bool)SHARED_FIELD_EX32(
s->regs[R_ROT_CREATOR_AUTH_CODESIGN_READ_LOCK], READ_LOCK);
break;
case OTP_PART_ROT_CREATOR_AUTH_STATE:
rdaccess =
(bool)SHARED_FIELD_EX32(s->regs[R_ROT_CREATOR_AUTH_STATE_READ_LOCK],
READ_LOCK);
rdaccess = (bool)
SHARED_FIELD_EX32(s->regs[R_ROT_CREATOR_AUTH_STATE_READ_LOCK],
READ_LOCK);
break;
case OTP_PART_SECRET0:
case OTP_PART_SECRET1:
@@ -852,16 +853,23 @@ static uint64_t ot_otp_eg_reg_read(void *opaque, hwaddr addr, unsigned size)
32u);
break;
case R_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0:
val32 = (uint32_t)ot_otp_eg_swcfg_get_part_digest(s, OTP_PART_ROT_CREATOR_AUTH_CODESIGN);
val32 = (uint32_t)
ot_otp_eg_swcfg_get_part_digest(s,
OTP_PART_ROT_CREATOR_AUTH_CODESIGN);
break;
case R_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1:
val32 = (uint32_t)(ot_otp_eg_swcfg_get_part_digest(s, OTP_PART_ROT_CREATOR_AUTH_CODESIGN) >> 32u);
val32 = (uint32_t)(ot_otp_eg_swcfg_get_part_digest(
s, OTP_PART_ROT_CREATOR_AUTH_CODESIGN) >>
32u);
break;
case R_ROT_CREATOR_AUTH_STATE_DIGEST_0:
val32 = (uint32_t)ot_otp_eg_swcfg_get_part_digest(s, OTP_PART_ROT_CREATOR_AUTH_STATE);
val32 = (uint32_t)
ot_otp_eg_swcfg_get_part_digest(s, OTP_PART_ROT_CREATOR_AUTH_STATE);
break;
case R_ROT_CREATOR_AUTH_STATE_DIGEST_1:
val32 = (uint32_t)(ot_otp_eg_swcfg_get_part_digest(s, OTP_PART_ROT_CREATOR_AUTH_STATE) >> 32u);
val32 = (uint32_t)(ot_otp_eg_swcfg_get_part_digest(
s, OTP_PART_ROT_CREATOR_AUTH_STATE) >>
32u);
break;
case R_HW_CFG0_DIGEST_0:
val32 = (uint32_t)ot_otp_eg_swcfg_get_part_digest(s, OTP_PART_HW_CFG0);
@@ -1168,7 +1176,8 @@ static void ot_otp_eg_load_hw_cfg(OtOTPEgState *s)
memset(hw_cfg->soc_dbg_state, 0, sizeof(hw_cfg->soc_dbg_state));
hw_cfg->en_sram_ifetch = (uint8_t)otp->data[R_EN_SRAM_IFETCH];

entropy_cfg->en_csrng_sw_app_read = (uint8_t)otp->data[R_EN_CSRNG_SW_APP_READ];
entropy_cfg->en_csrng_sw_app_read =
(uint8_t)otp->data[R_EN_CSRNG_SW_APP_READ];
}

static void ot_otp_eg_ctrl_get_lc_info(