[csrng/rtl] Remove final three prim_fifo_sync from data path

hw/ip/csrng/data/csrng.hjson

@@ -178,6 +178,9 @@
     { name: "MAIN_SM.FSM.SPARSE"
       desc: "The CSRNG main state machine uses a sparse state encoding."
     }
+    { name: "UPDRSP.FSM.SPARSE"
+      desc: "The CSRNG update response state machine uses a sparse state encoding."
+    }
     { name: "UPDATE.FSM.SPARSE"
       desc: "The CSRNG update state machine uses a sparse state encoding."
     }
@@ -188,13 +191,13 @@
       desc: "The CSRNG block output state machine uses a sparse state encoding."
     }
     { name: "GEN_CMD.CTR.REDUN"
-     desc: "The generate command uses a counter that is protected by a second counter that counts in the opposite direction."
+      desc: "The generate command uses a counter that is protected by a second counter that counts in the opposite direction."
     }
     { name: "DRBG_UPD.CTR.REDUN"
-     desc: "The ctr_drbg update algorithm uses a counter that is protected by a second counter that counts in the opposite direction."
+      desc: "The ctr_drbg update algorithm uses a counter that is protected by a second counter that counts in the opposite direction."
     }
     { name: "DRBG_GEN.CTR.REDUN"
-     desc: "The ctr_drbg generate algorithm uses a counter that is protected by a second counter that counts in the opposite direction."
+      desc: "The ctr_drbg generate algorithm uses a counter that is protected by a second counter that counts in the opposite direction."
     }
     { name: "CTRL.MUBI"
       desc: "Multi-bit field used for selection control."
@@ -728,33 +731,6 @@
                 This bit will stay set until the next reset.
                 '''
         }
-        { bits: "3",
-          name: "SFIFO_RCSTAGE_ERR",
-          desc: '''
-                This bit will be set to one when an error has been detected for the
-                rcstage FIFO. The type of error is reflected in the type status
-                bits (bits 28 through 30 of this register).
-                This bit will stay set until the next reset.
-                '''
-        }
-        { bits: "4",
-          name: "SFIFO_KEYVRC_ERR",
-          desc: '''
-                This bit will be set to one when an error has been detected for the
-                keyvrc FIFO. The type of error is reflected in the type status
-                bits (bits 28 through 30 of this register).
-                This bit will stay set until the next reset.
-                '''
-        }
-        { bits: "7",
-          name: "SFIFO_BENCACK_ERR",
-          desc: '''
-                This bit will be set to one when an error has been detected for the
-                bencack FIFO. The type of error is reflected in the type status
-                bits (bits 28 through 30 of this register).
-                This bit will stay set until the next reset.
-                '''
-        }
         { bits: "9",
           name: "SFIFO_FINAL_ERR",
           desc: '''
@@ -773,24 +749,6 @@
                 This bit will stay set until the next reset.
                 '''
         }
-        { bits: "11",
-          name: "SFIFO_GRCSTAGE_ERR",
-          desc: '''
-                This bit will be set to one when an error has been detected for the
-                grcstage FIFO. The type of error is reflected in the type status
-                bits (bits 28 through 30 of this register).
-                This bit will stay set until the next reset.
-                '''
-        }
-        { bits: "12",
-          name: "SFIFO_GGENREQ_ERR",
-          desc: '''
-                This bit will be set to one when an error has been detected for the
-                ggenreq FIFO. The type of error is reflected in the type status
-                bits (bits 28 through 30 of this register).
-                This bit will stay set until the next reset.
-                '''
-        }
         { bits: "13",
           name: "SFIFO_GADSTAGE_ERR",
           desc: '''
@@ -800,15 +758,6 @@
                 This bit will stay set until the next reset.
                 '''
         }
-        { bits: "14",
-          name: "SFIFO_GGENBITS_ERR",
-          desc: '''
-                This bit will be set to one when an error has been detected for the
-                ggenbits FIFO. The type of error is reflected in the type status
-                bits (bits 28 through 30 of this register).
-                This bit will stay set until the next reset.
-                '''
-        }
         { bits: "15",
           name: "SFIFO_CMDID_ERR",
           desc: '''
@@ -882,6 +831,15 @@
                 This bit will stay set until the next reset.
                 '''
         }
+        { bits: "27",
+          name: "DRBG_CMD_SM_ERR",
+          desc: '''
+                This bit will be set when the state machine in the ctr_drbg_cmd unit has entered
+                an illegal state.
+                This error will signal a fatal alert, and also an interrupt, if enabled.
+                This bit will stay set until the next reset.
+                '''
+        }
         { bits: "28",
           name: "FIFO_WRITE_ERR",
           desc: '''

hw/ip/csrng/data/csrng_sec_cm_testplan.hjson

@@ -66,6 +66,17 @@
       stage: V2S
       tests: ["csrng_sec_cm", "csrng_intr", "csrng_err"]
     }
+    {
+      name: sec_cm_updrsp_fsm_sparse
+      desc: '''
+            Verify the countermeasure(s) UPDRSP.FSM.SPARSE.
+            The csrng_intr and csrng_err tests verify that if the FSM state is forced to an illegal state encoding 1) this is reported with a cs_fatal_err interrupt in the INTR_STATE register and 2) the corresponding bit in the ERR_CODE register is set.
+            They currently don't check whether the DUT actually triggers a fatal alert.
+            Alert connection and triggering are verified through automated FPV.
+            '''
+      stage: V2S
+      tests: ["csrng_sec_cm", "csrng_intr", "csrng_err"]
+    }
     {
       name: sec_cm_update_fsm_sparse
       desc: '''

hw/ip/csrng/doc/interfaces.md

@@ -43,6 +43,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt
 | CSRNG.CONFIG.MUBI                   | Registers have multi-bit encoded fields.                                                                                                                                                                                                                            |
 | CSRNG.INTERSIG.MUBI                 | OTP signal used to enable software access to registers.                                                                                                                                                                                                             |
 | CSRNG.MAIN_SM.FSM.SPARSE            | The CSRNG main state machine uses a sparse state encoding.                                                                                                                                                                                                          |
+| CSRNG.UPDRSP.FSM.SPARSE             | The CSRNG update response state machine uses a sparse state encoding.                                                                                                                                                                                               |
 | CSRNG.UPDATE.FSM.SPARSE             | The CSRNG update state machine uses a sparse state encoding.                                                                                                                                                                                                        |
 | CSRNG.BLK_ENC.FSM.SPARSE            | The CSRNG block encrypt state machine uses a sparse state encoding.                                                                                                                                                                                                 |
 | CSRNG.OUTBLK.FSM.SPARSE             | The CSRNG block output state machine uses a sparse state encoding.                                                                                                                                                                                                  |

hw/ip/csrng/doc/registers.md

@@ -555,12 +555,12 @@ Writing a zero resets this status bit.
 Hardware detection of error conditions status register
 - Offset: `0x54`
 - Reset default: `0x0`
-- Reset mask: `0x77f0fe9b`
+- Reset mask: `0x7ff0a603`
 
 ### Fields
 
 ```wavejson
-{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 7}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_CMD_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
 ```
 
 |  Bits  |  Type  |  Reset  | Name                                                |
@@ -569,7 +569,7 @@ Hardware detection of error conditions status register
 |   30   |   ro   |   0x0   | [FIFO_STATE_ERR](#err_code--fifo_state_err)         |
 |   29   |   ro   |   0x0   | [FIFO_READ_ERR](#err_code--fifo_read_err)           |
 |   28   |   ro   |   0x0   | [FIFO_WRITE_ERR](#err_code--fifo_write_err)         |
-|   27   |        |         | Reserved                                            |
+|   27   |   ro   |   0x0   | [DRBG_CMD_SM_ERR](#err_code--drbg_cmd_sm_err)       |
 |   26   |   ro   |   0x0   | [CMD_GEN_CNT_ERR](#err_code--cmd_gen_cnt_err)       |
 |   25   |   ro   |   0x0   | [AES_CIPHER_SM_ERR](#err_code--aes_cipher_sm_err)   |
 |   24   |   ro   |   0x0   | [DRBG_UPDOB_SM_ERR](#err_code--drbg_updob_sm_err)   |
@@ -579,18 +579,12 @@ Hardware detection of error conditions status register
 |   20   |   ro   |   0x0   | [CMD_STAGE_SM_ERR](#err_code--cmd_stage_sm_err)     |
 | 19:16  |        |         | Reserved                                            |
 |   15   |   ro   |   0x0   | [SFIFO_CMDID_ERR](#err_code--sfifo_cmdid_err)       |
-|   14   |   ro   |   0x0   | [SFIFO_GGENBITS_ERR](#err_code--sfifo_ggenbits_err) |
+|   14   |        |         | Reserved                                            |
 |   13   |   ro   |   0x0   | [SFIFO_GADSTAGE_ERR](#err_code--sfifo_gadstage_err) |
-|   12   |   ro   |   0x0   | [SFIFO_GGENREQ_ERR](#err_code--sfifo_ggenreq_err)   |
-|   11   |   ro   |   0x0   | [SFIFO_GRCSTAGE_ERR](#err_code--sfifo_grcstage_err) |
+| 12:11  |        |         | Reserved                                            |
 |   10   |   ro   |   0x0   | [SFIFO_GBENCACK_ERR](#err_code--sfifo_gbencack_err) |
 |   9    |   ro   |   0x0   | [SFIFO_FINAL_ERR](#err_code--sfifo_final_err)       |
-|   8    |        |         | Reserved                                            |
-|   7    |   ro   |   0x0   | [SFIFO_BENCACK_ERR](#err_code--sfifo_bencack_err)   |
-|  6:5   |        |         | Reserved                                            |
-|   4    |   ro   |   0x0   | [SFIFO_KEYVRC_ERR](#err_code--sfifo_keyvrc_err)     |
-|   3    |   ro   |   0x0   | [SFIFO_RCSTAGE_ERR](#err_code--sfifo_rcstage_err)   |
-|   2    |        |         | Reserved                                            |
+|  8:2   |        |         | Reserved                                            |
 |   1    |   ro   |   0x0   | [SFIFO_GENBITS_ERR](#err_code--sfifo_genbits_err)   |
 |   0    |   ro   |   0x0   | [SFIFO_CMD_ERR](#err_code--sfifo_cmd_err)           |
 
@@ -612,6 +606,12 @@ this register) are asserted as a result of an error pulse generated from
 any full FIFO that has been received a write pulse.
 This bit will stay set until the next reset.
 
+### ERR_CODE . DRBG_CMD_SM_ERR
+This bit will be set when the state machine in the ctr_drbg_cmd unit has entered
+an illegal state.
+This error will signal a fatal alert, and also an interrupt, if enabled.
+This bit will stay set until the next reset.
+
 ### ERR_CODE . CMD_GEN_CNT_ERR
 This bit will be set to one when a mismatch in any of the hardened counters
 has been detected.
@@ -661,30 +661,12 @@ cmdid FIFO. The type of error is reflected in the type status
 bits (bits 28 through 30 of this register).
 This bit will stay set until the next reset.
 
-### ERR_CODE . SFIFO_GGENBITS_ERR
-This bit will be set to one when an error has been detected for the
-ggenbits FIFO. The type of error is reflected in the type status
-bits (bits 28 through 30 of this register).
-This bit will stay set until the next reset.
-
 ### ERR_CODE . SFIFO_GADSTAGE_ERR
 This bit will be set to one when an error has been detected for the
 gadstage FIFO. The type of error is reflected in the type status
 bits (bits 28 through 30 of this register).
 This bit will stay set until the next reset.
 
-### ERR_CODE . SFIFO_GGENREQ_ERR
-This bit will be set to one when an error has been detected for the
-ggenreq FIFO. The type of error is reflected in the type status
-bits (bits 28 through 30 of this register).
-This bit will stay set until the next reset.
-
-### ERR_CODE . SFIFO_GRCSTAGE_ERR
-This bit will be set to one when an error has been detected for the
-grcstage FIFO. The type of error is reflected in the type status
-bits (bits 28 through 30 of this register).
-This bit will stay set until the next reset.
-
 ### ERR_CODE . SFIFO_GBENCACK_ERR
 This bit will be set to one when an error has been detected for the
 gbencack FIFO. The type of error is reflected in the type status
@@ -697,24 +679,6 @@ final FIFO. The type of error is reflected in the type status
 bits (bits 28 through 30 of this register).
 This bit will stay set until the next reset.
 
-### ERR_CODE . SFIFO_BENCACK_ERR
-This bit will be set to one when an error has been detected for the
-bencack FIFO. The type of error is reflected in the type status
-bits (bits 28 through 30 of this register).
-This bit will stay set until the next reset.
-
-### ERR_CODE . SFIFO_KEYVRC_ERR
-This bit will be set to one when an error has been detected for the
-keyvrc FIFO. The type of error is reflected in the type status
-bits (bits 28 through 30 of this register).
-This bit will stay set until the next reset.
-
-### ERR_CODE . SFIFO_RCSTAGE_ERR
-This bit will be set to one when an error has been detected for the
-rcstage FIFO. The type of error is reflected in the type status
-bits (bits 28 through 30 of this register).
-This bit will stay set until the next reset.
-
 ### ERR_CODE . SFIFO_GENBITS_ERR
 This bit will be set to one when an error has been detected for the
 command stage genbits FIFO. The type of error is reflected in the type status

hw/ip/csrng/dv/cov/csrng_cov_if.sv

@@ -243,15 +243,15 @@ interface csrng_cov_if (
       // If ERR_CODE register has SFIFO related field set, it also needs to set at least one
       // FIFO_*_ERR field.
       illegal_bins illegal = !binsof(cp_err_codes) intersect { CMD_STAGE_SM_ERR, MAIN_SM_ERR,
-                                                               DRBG_GEN_SM_ERR, DRBG_UPDBE_SM_ERR,
-                                                               DRBG_UPDOB_SM_ERR, AES_CIPHER_SM_ERR,
-                                                               CMD_GEN_CNT_ERR } &&
-                             binsof(cp_fifo_err_type) intersect { 0 };
+                                                               DRBG_CMD_SM_ERR, DRBG_GEN_SM_ERR,
+                                                               DRBG_UPDBE_SM_ERR, DRBG_UPDOB_SM_ERR,
+                                                               AES_CIPHER_SM_ERR, CMD_GEN_CNT_ERR }
+                             && binsof(cp_fifo_err_type) intersect { 0 };
 
       ignore_bins ignore = binsof(cp_err_codes) intersect { CMD_STAGE_SM_ERR, MAIN_SM_ERR,
-                                                            DRBG_GEN_SM_ERR, DRBG_UPDBE_SM_ERR,
-                                                            DRBG_UPDOB_SM_ERR, AES_CIPHER_SM_ERR,
-                                                            CMD_GEN_CNT_ERR };
+                                                            DRBG_CMD_SM_ERR, DRBG_GEN_SM_ERR,
+                                                            DRBG_UPDBE_SM_ERR, DRBG_UPDOB_SM_ERR,
+                                                            AES_CIPHER_SM_ERR, CMD_GEN_CNT_ERR };
     }
 
     cp_csrng_aes_fsm_err: coverpoint
@@ -365,6 +365,16 @@ interface csrng_cov_if (
       ignore_bins invalid = binsof(cp_acmd) intersect { INV, GENB, GENU };
     }
 
+    clen_glen_cross: cross cp_acmd, cp_clen, cp_glen {
+      bins gen_glen_clen = binsof(cp_acmd) intersect { GEN } &&
+                           binsof(cp_clen) intersect { [1:$] } &&
+                           binsof(cp_glen) intersect { [2:$] };
+      // We are only interested in Generate commands in this crosspoint (and glen has no meaning
+      // for all other commands)
+      ignore_bins ignore_other_cmds = binsof(cp_acmd) intersect
+                                      { INS, UNI, UPD, RES, INV, GENB, GENU };
+    }
+
     flags_clen_acmd_cross: cross cp_acmd, cp_flags, cp_clen {
       // Use only Entropy Source seed
       bins ins_only_entropy_src_seed = binsof(cp_flags) intersect { MuBi4False } &&