Simulation Failure in 4-bit Multiplier Circuit

[shimoshida]

Describe the bug
When implementing a 4-bit multiplier circuit on an FPGA fabric generated using OpenFPGA and running a simulation, the simulation fails. The same implementation works correctly for 2-bit and 3-bit multiplier circuits, and no issues were observed in those cases.

• OpenFPGA flow

To Reproduce
Steps to reproduce the behavior:

1. Clone OpenFPGA repository and checkout current master
   commit id: 55c2ccf50798645694204434936c38f86b14611b

2. Change or add some files relevant to generate_fabric task

• task.conf

Details

[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
# fpga_flow=yosys_vpr
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml 

[OpenFPGA_SHELL]
# openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga

openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
# Use a absolute path for the Verilog netlists to be generated
# This is designed to allow the test case 'basic_tests/generate_testbench'
# to use the Verilog netlists along with testbenches in HDL simulation
openfpga_verilog_output_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=20

[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml

[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult4/mult4.blif

[SYNTHESIS_PARAM]
bench0_top = mult4
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult4/mult4.v
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult4/mult4.act

[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

• benchmark: mult4

Details

# Benchmark "mult4" written by ABC on Sat Jan 24 18:54:44 2026
.model mult4
.inputs A[0] A[1] A[2] A[3] B[0] B[1] B[2] B[3] 
.outputs Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] 
.names B[0] A[0] Y[0]
11 1
.names B[0] A[1] B[1] A[0] Y[1]
-011 1
0-11 1
11-0 1
110- 1
.names A[2] B[2] A[1] B[1] B[0] A[0] Y[2]
---000 0
--0-00 0
-0-00- 0
-00-0- 0
-11101 0
0--0-0 0
0-0--0 0
00--11 0
1-1110 0
11--11 0
.names new_$abc$328$new_n24 new_$abc$328$new_n25 new_$abc$328$new_n23 \
 new_$abc$328$new_n22 new_$abc$328$new_n27 new_$abc$328$new_n26 Y[4]
-00001 1
-00010 1
-01100 1
-01111 1
-10100 1
-10111 1
-11000 1
-11011 1
0-0100 1
0-0111 1
0-1000 1
0-1011 1
01-000 1
01-011 1
011101 1
011110 1
1-0001 1
1-0010 1
1-1100 1
1-1111 1
10-001 1
10-010 1
100-01 1
100-10 1
.names B[2] A[2] A[0] A[1] B[1] B[0] new_$abc$328$new_n22
001111 1
111111 1
.names B[3] A[0] new_$abc$328$new_n23
11 1
.names A[2] B[0] B[1] A[1] B[2] A[0] new_$abc$328$new_n24
--1111 0
11--11 0
1111-- 0
.names B[0] A[2] B[1] A[3] B[2] A[1] new_$abc$328$new_n25
--0011 1
-0-011 1
-110-0 1
-1100- 1
0-0-11 1
00--11 1
011--0 1
011-0- 1
1-01-0 1
1-010- 1
10-1-0 1
10-10- 1
111111 1
.names B[3] A[1] new_$abc$328$new_n26
11 1
.names B[0] A[1] A[3] B[2] A[2] B[1] new_$abc$328$new_n27
---0-0 0
--0-0- 0
--00-- 0
-0--00 0
-10--1 0
0---00 0
001111 0
1--01- 0
11-101 0
111-10 0
.names new_$abc$328$new_n33 new_$abc$328$new_n30 new_$abc$328$new_n29 Y[5]
-10 1
001 1
1-0 1
.names new_$abc$328$new_n25 new_$abc$328$new_n23 new_$abc$328$new_n22 \
 new_$abc$328$new_n24 new_$abc$328$new_n26 new_$abc$328$new_n27 \
 new_$abc$328$new_n29
---100 1
---111 1
--0-00 1
--0-11 1
-0--00 1
-0--11 1
-001-- 1
0---00 1
0---11 1
0-01-- 1
00-1-- 1
000--- 1
.names new_$abc$328$new_n27 new_$abc$328$new_n26 new_$abc$328$new_n31 \
 new_$abc$328$new_n32 new_$abc$328$new_n30
--11 1
11-1 1
.names B[0] A[1] A[2] B[1] A[3] B[2] new_$abc$328$new_n31
-11101 1
1-1110 1
110111 1
111011 1
.names B[1] B[2] A[3] A[2] B[3] new_$abc$328$new_n32
--011 1
-0-11 1
-110- 1
011-0 1
1--11 1
.names new_$abc$328$new_n27 new_$abc$328$new_n26 new_$abc$328$new_n32 \
 new_$abc$328$new_n31 new_$abc$328$new_n33
-000 1
0-00 1
.names new_$abc$328$new_n33 new_$abc$328$new_n35 B[3] A[3] \
 new_$abc$328$new_n30 new_$abc$328$new_n36 Y[6]
---011 1
--0-11 1
--1110 1
-0-000 1
-00-00 1
-01101 1
01-0-1 1
010--1 1
0111-0 1
1--000 1
1-0-00 1
1-1101 1
.names new_$abc$328$new_n27 new_$abc$328$new_n26 new_$abc$328$new_n24 \
 new_$abc$328$new_n25 new_$abc$328$new_n23 new_$abc$328$new_n35
---00 0
--1-0 0
--10- 0
00--- 0
11--- 0
.names B[3] B[1] A[3] A[2] B[2] new_$abc$328$new_n36
-1111 0
1-111 0
.names new_$abc$328$new_n25 new_$abc$328$new_n24 new_$abc$328$new_n23 \
 new_$abc$328$new_n22 Y[3]
0000 1
0011 1
0101 1
0110 1
1001 1
1010 1
1100 1
1111 1
.names new_$abc$328$new_n30 new_$abc$328$new_n33 new_$abc$328$new_n35 \
 new_$abc$328$new_n36 A[3] B[3] Y[7]
---011 1
-01-11 1
-010-- 1
1---11 1
1--0-- 1
.end

3. Execute OpenFPGA task or your own example:
   python openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric

4. Fix generated verilog files in SRC directory

• Some modules: nettype none is replaced with wire
• Test bench

Details

//-------------------------------------------
//	FPGA Synthesizable Verilog Netlist
//	Description: FPGA Verilog full testbench for top-level netlist of design: mult4
//	Author: Xifan TANG
//	Organization: University of Utah
//	Date: Sat Jan 24 19:10:26 2026
//-------------------------------------------
//----- Default net type -----
`default_nettype wire

module mult4_autocheck_top_tb;
// ----- Local wires for global ports of FPGA fabric -----
wire [0:0] pReset;
wire [0:0] prog_clk;
wire [0:0] set;
wire [0:0] reset;
wire [0:0] clk;

// ----- Local wires for I/Os of FPGA fabric -----
wire [0:63] gfpga_pad_GPIO_PAD;



reg [0:0] __config_done__;
wire [0:0] __config_all_done__;
wire [0:0] __prog_clock__;
reg [0:0] __prog_clock___reg__;
wire [0:0] __op_clock__;
reg [0:0] __op_clock___reg__;
reg [0:0] __prog_reset__;
reg [0:0] __prog_set_;
reg [0:0] __greset__;
reg [0:0] __gset__;
// ---- Configuration-chain head -----
reg [0:0] ccff_head;
// ---- Configuration-chain tail -----
wire [0:0] ccff_tail;
// ----- Shared inputs -------
	reg [0:0] A_0__shared_input;
	reg [0:0] A_1__shared_input;
	reg [0:0] A_2__shared_input;
	reg [0:0] A_3__shared_input;
	reg [0:0] B_0__shared_input;
	reg [0:0] B_1__shared_input;
	reg [0:0] B_2__shared_input;
	reg [0:0] B_3__shared_input;

	wire [3:0] A_shared_input = {A_3__shared_input,
			 A_2__shared_input,
			 A_1__shared_input,
			 A_0__shared_input};

	wire [3:0] B_shared_input = {B_3__shared_input,
			 B_2__shared_input,
			 B_1__shared_input,
			 B_0__shared_input};
// ----- FPGA fabric outputs -------
	wire [0:0] Y_0__fpga;
	wire [0:0] Y_1__fpga;
	wire [0:0] Y_2__fpga;
	wire [0:0] Y_3__fpga;
	wire [0:0] Y_4__fpga;
	wire [0:0] Y_5__fpga;
	wire [0:0] Y_6__fpga;
	wire [0:0] Y_7__fpga;
	wire [7:0] Y_fpga = {Y_7__fpga,
		     Y_6__fpga,
		     Y_5__fpga,
		     Y_4__fpga,
		     Y_3__fpga,
		     Y_2__fpga,
		     Y_1__fpga,
		     Y_0__fpga};

// ----- Benchmark outputs -------
	wire [0:0] Y_0__benchmark;
	wire [0:0] Y_1__benchmark;
	wire [0:0] Y_2__benchmark;
	wire [0:0] Y_3__benchmark;
	wire [0:0] Y_4__benchmark;
	wire [0:0] Y_5__benchmark;
	wire [0:0] Y_6__benchmark;
	wire [0:0] Y_7__benchmark;
	wire [7:0] Y_benchmark = {Y_7__benchmark,
		     Y_6__benchmark,
		     Y_5__benchmark,
		     Y_4__benchmark,
		     Y_3__benchmark,
		     Y_2__benchmark,
		     Y_1__benchmark,
		     Y_0__benchmark};

// ----- Output vectors checking flags -------
	reg [0:0] Y_0__flag;
	reg [0:0] Y_1__flag;
	reg [0:0] Y_2__flag;
	reg [0:0] Y_3__flag;
	reg [0:0] Y_4__flag;
	reg [0:0] Y_5__flag;
	reg [0:0] Y_6__flag;
	reg [0:0] Y_7__flag;

// ----- Error counter: Deposit an error for config_done signal is not raised at the beginning -----
	integer nb_error= 1;
// ----- Number of clock cycles in configuration phase: 8417 -----
// ----- Begin configuration done signal generation -----
initial
	begin
		__config_done__[0] = 1'b0;
	end

// ----- End configuration done signal generation -----

// ----- Begin raw programming clock signal generation -----
initial
	begin
		__prog_clock___reg__[0] = 1'b0;
	end
always
	begin
		#5	__prog_clock___reg__[0] = ~__prog_clock___reg__[0];
	end

// ----- End raw programming clock signal generation -----

// ----- Actual programming clock is triggered only when __config_done__ and __prog_reset__ are disabled -----
	assign __prog_clock__[0] = __prog_clock___reg__[0] & (~__config_done__[0]) & (~__prog_reset__[0]);

	assign __config_all_done__[0] = __config_done__[0];
// ----- Begin raw operating clock signal generation -----
initial
	begin
		__op_clock___reg__[0] = 1'b0;
	end
always wait(~__greset__)
	begin
		#1.761053801	__op_clock___reg__[0] = ~__op_clock___reg__[0];
	end

// ----- End raw operating clock signal generation -----
// ----- Actual operating clock is triggered only when __config_all_done__ is enabled -----
	assign __op_clock__[0] = __op_clock___reg__[0] & __config_all_done__[0];

// ----- Begin programming reset signal generation -----
initial
	begin
		__prog_reset__[0] = 1'b1;
	#10	__prog_reset__[0] = 1'b0;
	end

// ----- End programming reset signal generation -----

// ----- Begin programming set signal generation -----
initial
	begin
		__prog_set_[0] = 1'b1;
	#10	__prog_set_[0] = 1'b0;
	end

// ----- End programming set signal generation -----

// ----- Begin operating reset signal generation -----
// ----- Reset signal is enabled until the first clock cycle in operation phase -----
initial
	begin
		__greset__[0] = 1'b1;
	wait(__config_all_done__)
	#3.522107601	__greset__[0] = 1'b1;
	#7.044215202	__greset__[0] = 1'b0;
	end

// ----- End operating reset signal generation -----
// ----- Begin operating set signal generation: always disabled -----
initial
	begin
		__gset__[0] = 1'b0;
	end

// ----- End operating set signal generation: always disabled -----

// ----- Begin connecting global ports of FPGA fabric to stimuli -----
	assign clk[0] = __op_clock__[0];
	assign prog_clk[0] = __prog_clock__[0];
	assign reset[0] = __greset__[0];
	assign pReset[0] = __prog_reset__[0];
	assign set[0] = __gset__[0];
// ----- End connecting global ports of FPGA fabric to stimuli -----
// ----- FPGA top-level module to be capsulated -----
	fpga_top FPGA_DUT (
		.pReset(pReset[0]),
		.prog_clk(prog_clk[0]),
		.set(set[0]),
		.reset(reset[0]),
		.clk(clk[0]),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0:63]),
		.ccff_head(ccff_head[0]),
		.ccff_tail(ccff_tail[0]));

// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
// ----- Blif Benchmark input A_0_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[12] -----
	assign gfpga_pad_GPIO_PAD[12] = A_0__shared_input[0];

// ----- Blif Benchmark input A_1_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[9] -----
	assign gfpga_pad_GPIO_PAD[9] = A_1__shared_input[0];

// ----- Blif Benchmark input A_2_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[32] -----
	assign gfpga_pad_GPIO_PAD[32] = A_2__shared_input[0];

// ----- Blif Benchmark input A_3_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[34] -----
	assign gfpga_pad_GPIO_PAD[34] = A_3__shared_input[0];

// ----- Blif Benchmark input B_0_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[39] -----
	assign gfpga_pad_GPIO_PAD[39] = B_0__shared_input[0];

// ----- Blif Benchmark input B_1_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[36] -----
	assign gfpga_pad_GPIO_PAD[36] = B_1__shared_input[0];

// ----- Blif Benchmark input B_2_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[11] -----
	assign gfpga_pad_GPIO_PAD[11] = B_2__shared_input[0];

// ----- Blif Benchmark input B_3_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[38] -----
	assign gfpga_pad_GPIO_PAD[38] = B_3__shared_input[0];

// ----- Blif Benchmark output Y_0_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[37] -----
	assign Y_0__fpga[0] = gfpga_pad_GPIO_PAD[37];

// ----- Blif Benchmark output Y_1_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[19] -----
	assign Y_1__fpga[0] = gfpga_pad_GPIO_PAD[19];

// ----- Blif Benchmark output Y_2_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[27] -----
	assign Y_2__fpga[0] = gfpga_pad_GPIO_PAD[27];

// ----- Blif Benchmark output Y_3_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[35] -----
	assign Y_3__fpga[0] = gfpga_pad_GPIO_PAD[35];

// ----- Blif Benchmark output Y_4_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[33] -----
	assign Y_4__fpga[0] = gfpga_pad_GPIO_PAD[33];

// ----- Blif Benchmark output Y_5_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[8] -----
	assign Y_5__fpga[0] = gfpga_pad_GPIO_PAD[8];

// ----- Blif Benchmark output Y_6_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[14] -----
	assign Y_6__fpga[0] = gfpga_pad_GPIO_PAD[14];

// ----- Blif Benchmark output Y_7_ is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[29] -----
	assign Y_7__fpga[0] = gfpga_pad_GPIO_PAD[29];

// ----- Wire unused FPGA I/Os to constants -----
	assign gfpga_pad_GPIO_PAD[0] = 1'b0;
	assign gfpga_pad_GPIO_PAD[1] = 1'b0;
	assign gfpga_pad_GPIO_PAD[2] = 1'b0;
	assign gfpga_pad_GPIO_PAD[3] = 1'b0;
	assign gfpga_pad_GPIO_PAD[4] = 1'b0;
	assign gfpga_pad_GPIO_PAD[5] = 1'b0;
	assign gfpga_pad_GPIO_PAD[6] = 1'b0;
	assign gfpga_pad_GPIO_PAD[7] = 1'b0;
	assign gfpga_pad_GPIO_PAD[10] = 1'b0;
	assign gfpga_pad_GPIO_PAD[13] = 1'b0;
	assign gfpga_pad_GPIO_PAD[15] = 1'b0;
	assign gfpga_pad_GPIO_PAD[16] = 1'b0;
	assign gfpga_pad_GPIO_PAD[17] = 1'b0;
	assign gfpga_pad_GPIO_PAD[18] = 1'b0;
	assign gfpga_pad_GPIO_PAD[20] = 1'b0;
	assign gfpga_pad_GPIO_PAD[21] = 1'b0;
	assign gfpga_pad_GPIO_PAD[22] = 1'b0;
	assign gfpga_pad_GPIO_PAD[23] = 1'b0;
	assign gfpga_pad_GPIO_PAD[24] = 1'b0;
	assign gfpga_pad_GPIO_PAD[25] = 1'b0;
	assign gfpga_pad_GPIO_PAD[26] = 1'b0;
	assign gfpga_pad_GPIO_PAD[28] = 1'b0;
	assign gfpga_pad_GPIO_PAD[30] = 1'b0;
	assign gfpga_pad_GPIO_PAD[31] = 1'b0;
	assign gfpga_pad_GPIO_PAD[40] = 1'b0;
	assign gfpga_pad_GPIO_PAD[41] = 1'b0;
	assign gfpga_pad_GPIO_PAD[42] = 1'b0;
	assign gfpga_pad_GPIO_PAD[43] = 1'b0;
	assign gfpga_pad_GPIO_PAD[44] = 1'b0;
	assign gfpga_pad_GPIO_PAD[45] = 1'b0;
	assign gfpga_pad_GPIO_PAD[46] = 1'b0;
	assign gfpga_pad_GPIO_PAD[47] = 1'b0;
	assign gfpga_pad_GPIO_PAD[48] = 1'b0;
	assign gfpga_pad_GPIO_PAD[49] = 1'b0;
	assign gfpga_pad_GPIO_PAD[50] = 1'b0;
	assign gfpga_pad_GPIO_PAD[51] = 1'b0;
	assign gfpga_pad_GPIO_PAD[52] = 1'b0;
	assign gfpga_pad_GPIO_PAD[53] = 1'b0;
	assign gfpga_pad_GPIO_PAD[54] = 1'b0;
	assign gfpga_pad_GPIO_PAD[55] = 1'b0;
	assign gfpga_pad_GPIO_PAD[56] = 1'b0;
	assign gfpga_pad_GPIO_PAD[57] = 1'b0;
	assign gfpga_pad_GPIO_PAD[58] = 1'b0;
	assign gfpga_pad_GPIO_PAD[59] = 1'b0;
	assign gfpga_pad_GPIO_PAD[60] = 1'b0;
	assign gfpga_pad_GPIO_PAD[61] = 1'b0;
	assign gfpga_pad_GPIO_PAD[62] = 1'b0;
	assign gfpga_pad_GPIO_PAD[63] = 1'b0;

// ----- Reference Benchmark Instanication -------
	mult4 REF_DUT(
		.A(A_shared_input),
		.B(B_shared_input),
		.Y(Y_benchmark)
	);
// ----- End reference Benchmark Instanication -------

// ----- Begin bitstream loading during configuration phase -----
`define BITSTREAM_LENGTH 8416
`define BITSTREAM_WIDTH 1
// ----- Virtual memory to store the bitstream from external file -----
reg [0:`BITSTREAM_WIDTH - 1] bit_mem[0:`BITSTREAM_LENGTH - 1];
reg [$clog2(`BITSTREAM_LENGTH):0] bit_index;
// ----- Registers used for fast configuration logic -----
reg [$clog2(`BITSTREAM_LENGTH):0] ibit;
reg [0:0] skip_bits;
// ----- Preload bitstream file to a virtual memory -----
initial begin
	$readmemb("fabric_bitstream.bit", bit_mem);
// ----- Configuration chain default input -----
	ccff_head[0] <= 1'b0;
	bit_index <= 0;
	skip_bits[0] <= 1'b0;
	for (ibit = 0; ibit < `BITSTREAM_LENGTH + 1; ibit = ibit + 1) begin
		if (1'b0 == bit_mem[ibit]) begin
			if (1'b1 == skip_bits[0]) begin
				bit_index <= bit_index + 1;
			end
		end else begin
			skip_bits[0] <= 1'b0;
		end
	end
end
// ----- 'else if' condition is required by Modelsim to synthesis the Verilog correctly -----
always @(negedge __prog_clock___reg__[0]) begin
	if (bit_index >= `BITSTREAM_LENGTH) begin
		__config_done__[0] <= 1'b1;
	end else if (bit_index >= 0 && bit_index < `BITSTREAM_LENGTH) begin
		ccff_head[0] <= bit_mem[bit_index];
		bit_index <= bit_index + 1;
	end
end
// ----- End bitstream loading during configuration phase -----
// ----- Begin reset signal generation -----
// ----- Input Initialization -------
	initial begin
		A_0__shared_input <= 1'b0;
		A_1__shared_input <= 1'b0;
		A_2__shared_input <= 1'b0;
		A_3__shared_input <= 1'b0;
		B_0__shared_input <= 1'b0;
		B_1__shared_input <= 1'b0;
		B_2__shared_input <= 1'b0;
		B_3__shared_input <= 1'b0;

		Y_0__flag[0] <= 1'b0;
		Y_1__flag[0] <= 1'b0;
		Y_2__flag[0] <= 1'b0;
		Y_3__flag[0] <= 1'b0;
		Y_4__flag[0] <= 1'b0;
		Y_5__flag[0] <= 1'b0;
		Y_6__flag[0] <= 1'b0;
		Y_7__flag[0] <= 1'b0;
	end

// ----- Input Stimulus -------
	always@(negedge __op_clock__[0]) begin
		A_0__shared_input <= $random;
		A_1__shared_input <= $random;
		A_2__shared_input <= $random;
		A_3__shared_input <= $random;
		B_0__shared_input <= $random;
		B_1__shared_input <= $random;
		B_2__shared_input <= $random;
		B_3__shared_input <= $random;
	end

// ----- Begin checking output vectors -------
// ----- Skip the first falling edge of clock, it is for initialization -------
	reg [0:0] sim_start;

	always@(negedge __op_clock__[0]) begin
		if (1'b1 == sim_start[0]) begin
			sim_start[0] <= ~sim_start[0];
		end else 
			if (1'b1 == __config_all_done__) begin
			if(!(Y_0__fpga === Y_0__benchmark) && !(Y_0__benchmark === 1'bx)) begin
				Y_0__flag <= 1'b1;
			end else begin
				Y_0__flag<= 1'b0;
			end
			if(!(Y_1__fpga === Y_1__benchmark) && !(Y_1__benchmark === 1'bx)) begin
				Y_1__flag <= 1'b1;
			end else begin
				Y_1__flag<= 1'b0;
			end
			if(!(Y_2__fpga === Y_2__benchmark) && !(Y_2__benchmark === 1'bx)) begin
				Y_2__flag <= 1'b1;
			end else begin
				Y_2__flag<= 1'b0;
			end
			if(!(Y_3__fpga === Y_3__benchmark) && !(Y_3__benchmark === 1'bx)) begin
				Y_3__flag <= 1'b1;
			end else begin
				Y_3__flag<= 1'b0;
			end
			if(!(Y_4__fpga === Y_4__benchmark) && !(Y_4__benchmark === 1'bx)) begin
				Y_4__flag <= 1'b1;
			end else begin
				Y_4__flag<= 1'b0;
			end
			if(!(Y_5__fpga === Y_5__benchmark) && !(Y_5__benchmark === 1'bx)) begin
				Y_5__flag <= 1'b1;
			end else begin
				Y_5__flag<= 1'b0;
			end
			if(!(Y_6__fpga === Y_6__benchmark) && !(Y_6__benchmark === 1'bx)) begin
				Y_6__flag <= 1'b1;
			end else begin
				Y_6__flag<= 1'b0;
			end
			if(!(Y_7__fpga === Y_7__benchmark) && !(Y_7__benchmark === 1'bx)) begin
				Y_7__flag <= 1'b1;
			end else begin
				Y_7__flag<= 1'b0;
			end
		end
	end

	always@(posedge Y_0__flag) begin
		if(Y_0__flag) begin
			nb_error = nb_error + 1;
			$display("Mismatch on Y_0__fpga at time = %t", $realtime);
		end
	end

	always@(posedge Y_1__flag) begin
		if(Y_1__flag) begin
			nb_error = nb_error + 1;
			$display("Mismatch on Y_1__fpga at time = %t", $realtime);
		end
	end

	always@(posedge Y_2__flag) begin
		if(Y_2__flag) begin
			nb_error = nb_error + 1;
			$display("Mismatch on Y_2__fpga at time = %t", $realtime);
		end
	end

	always@(posedge Y_3__flag) begin
		if(Y_3__flag) begin
			nb_error = nb_error + 1;
			$display("Mismatch on Y_3__fpga at time = %t", $realtime);
		end
	end

	always@(posedge Y_4__flag) begin
		if(Y_4__flag) begin
			nb_error = nb_error + 1;
			$display("Mismatch on Y_4__fpga at time = %t", $realtime);
		end
	end

	always@(posedge Y_5__flag) begin
		if(Y_5__flag) begin
			nb_error = nb_error + 1;
			$display("Mismatch on Y_5__fpga at time = %t", $realtime);
		end
	end

	always@(posedge Y_6__flag) begin
		if(Y_6__flag) begin
			nb_error = nb_error + 1;
			$display("Mismatch on Y_6__fpga at time = %t", $realtime);
		end
	end

	always@(posedge Y_7__flag) begin
		if(Y_7__flag) begin
			nb_error = nb_error + 1;
			$display("Mismatch on Y_7__fpga at time = %t", $realtime);
		end
	end


// ----- Configuration done must be raised in the end -------
	always@(posedge __config_all_done__[0]) begin
		nb_error = nb_error - 1;
	end

// ----- Begin output waveform to VCD file-------
	initial begin
		$dumpfile("mult4_formal.vcd");
		$dumpvars(1, mult4_autocheck_top_tb);
	end
// ----- END output waveform to VCD file -------

initial begin
	sim_start[0] <= 1'b1;
	$timeformat(-9, 2, "ns", 20);
	$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
	#84240
	if(nb_error == 0) begin
		$display("Simulation Succeed");
	end else begin
		$display("Simulation Failed with %d error(s)", nb_error);
	end
	$finish;
end

endmodule
// ----- END Verilog module for mult4_autocheck_top_tb -----

//----- Default net type -----
`default_nettype wire

4. See error

Expected behavior
Simulation Succeeds

Screenshots
Simulation via Vivado 2024.1

Enviornment (please complete the following information):

• OS: Ubuntu 22.04.5 LTS
• Compiler:N/A
• Version: Current master

[tangxifan]

@shimoshida Thank you for trying OpenFPGA.

• The testcase generate_fabric only writes out Verilog netlists of the FPGA fabric. It does not write out bitstream and testbenches which enable the simulation you mentioned here.
• The testcase generate_fabric is based on a fix-sized mini FPGA fabric, which contains only 4 CLBs and 20 routing tracks per channel. Even simple benchmark like mult4 may not fit there.

Therefore,

• Can you share how to reproduce the simulation errors in details?
• Can you double check if mult4 has successfully passed VPR flow and bitstream is generated? Please ensure that the FPGA size and routing channel width is not changed.

I would like to help and add your test to OpenFPGA's regression test. This will help other users in my view.

[shimoshida]

@tangxifan Thank you for your comments.

The testcase generate_fabric only writes out Verilog netlists of the FPGA fabric. It does not write out bitstream and testbenches which enable the simulation you mentioned here.

As you said, original generate_fabric task does not output test bench and bitstream.
I forgot to share the modified OpenFPGA shell. Sorry for the inconvenience.

The testcase generate_fabric is based on a fix-sized mini FPGA fabric, which contains only 4 CLBs and 20 routing tracks per channel. Even simple benchmark like mult4 may not fit there.

I am checking openfpgashell.log, but it doesn’t appear that anything is failing.
(This is an answer of your question "Can you double check if mult4 has successfully passed VPR flow and bitstream is generated? Please ensure that the FPGA size and routing channel width is not changed.")

openfpgashell.log

/home/moshida/OpenFPGA/build/openfpga/openfpga -batch -f mult4_run.openfpga
Reading script file mult4_run.openfpga...

            ___                   _____ ____   ____    _     
           / _ \ _ __   ___ _ __ |  ___|  _ \ / ___|  / \    
          | | | | '_ \ / _ \ '_ \| |_  | |_) | |  _  / _ \   
          | |_| | |_) |  __/ | | |  _| |  __/| |_| |/ ___ \  
           \___/| .__/ \___|_| |_|_|   |_|    \____/_/   \_\ 
                |_|                                          

               OpenFPGA: An Open-source FPGA IP Generator
                     Versatile Place and Route (VPR)
                           FPGA-Verilog
                           FPGA-SPICE
                           FPGA-SDC
                           FPGA-Bitstream

             This is a free software under the MIT License

             Copyright (c) 2018 LNIS - The University of Utah

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.



Command line to execute: vpr /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run026/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_tileable_40nm.xml mult4.blif --clock_modeling route --device 2x2 --route_chan_width 20
VPR FPGA Placement and Routing.
Version: 9.0.0-dev+v8.0.0-14872-gd3c57bc97
Revision: v8.0.0-14872-gd3c57bc97
Compiled: 2026-01-15T16:57:17
Compiler: GNU 11.4.0 on Linux-6.8.0-87-generic x86_64
Build Info: release IPO VTR_ASSERT_LEVEL=2

University of Toronto
verilogtorouting.org
vtr-users@googlegroups.com
This is free open source code under MIT license.

VPR was run with the following command-line:
vpr /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run026/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_tileable_40nm.xml mult4.blif --clock_modeling route --device 2x2 --route_chan_width 20

Using up to 1 parallel worker(s)

Architecture file: /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run026/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_tileable_40nm.xml
Circuit name: mult4

# Loading Architecture Description
Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 3: Model 'frac_lut6' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 4: Model 'frac_lut6' output port 'lut6_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 5: Model 'frac_lut6' output port 'lut5_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
mode 'io[physical]' is defined by user to be disabled in packing
mode 'fle[physical]' is defined by user to be disabled in packing
mode 'fabric[default]' is defined by user to be disabled in packing
mode 'frac_logic[default]' is defined by user to be disabled in packing
# Loading Architecture Description took 0.00 seconds (max_rss 21.2 MiB, delta_rss +2.2 MiB)

Timing analysis: ON
Circuit netlist file: mult4.net
Circuit placement file: mult4.place
Circuit routing file: mult4.route
Circuit SDC file: mult4.sdc
Vpr floorplanning constraints file: not specified

Packer: ENABLED
Placer: ENABLED
Analytical Placer: DISABLED
Router: ENABLED
Analysis: SKIP IF PRIOR FAIL

VPR was run with the following options:

NetlistOpts.absorb_buffer_luts            : true
NetlistOpts.sweep_dangling_primary_ios    : true
NetlistOpts.sweep_dangling_nets           : true
NetlistOpts.sweep_dangling_blocks         : true
NetlistOpts.sweep_constant_primary_outputs: false
NetlistOpts.netlist_verbosity             : 1
NetlistOpts.const_gen_inference           : COMB_SEQ

PackerOpts.allow_unrelated_clustering: auto
PackerOpts.timing_gain_weight: 0.750000
PackerOpts.connection_gain_weight: 0.900000
PackerOpts.cluster_seed_type: BLEND2
PackerOpts.connection_driven: true
PackerOpts.timing_driven: true
PackerOpts.target_external_pin_util: auto

PlacerOpts.place_freq: PLACE_ONCE
PlacerOpts.place_algorithm: CRITICALITY_TIMING_PLACE
PlacerOpts.pad_loc_type: FREE
PlacerOpts.constraints_file: No constraints file given
PlacerOpts.place_chan_width: 20
PlacerOpts.inner_loop_recompute_divider: 0
PlacerOpts.recompute_crit_iter: 1
PlacerOpts.timing_tradeoff: 0.500000
PlacerOpts.td_place_exp_first: 1.000000
PlacerOpts.td_place_exp_last: 8.000000
PlacerOpts.delay_offset: 0.000000
PlacerOpts.delay_ramp_delta_threshold: -1
PlacerOpts.delay_ramp_slope: 0.000000
PlacerOpts.tsu_rel_margin: 1.000000
PlacerOpts.tsu_abs_margin: 0.000000
PlacerOpts.post_place_timing_report_file: 
PlacerOpts.allowed_tiles_for_delay_model: 
PlacerOpts.delay_model_reducer: MIN
PlacerOpts.delay_model_type: SIMPLE
PlacerOpts.rlim_escape_fraction: 0.000000
PlacerOpts.move_stats_file: 
PlacerOpts.placement_saves_per_temperature: 0
PlacerOpts.effort_scaling: CIRCUIT
PlacerOpts.place_delta_delay_matrix_calculation_method: ASTAR_ROUTE
PlaceOpts.seed: 1
AnnealSched.type: AUTO_SCHED
AnnealSched.inner_num: 0.500000

RouterOpts.route_type: DETAILED
RouterOpts.flat_routing: false
RouterOpts.choke_points: on
RouterOpts.router_algorithm: TIMING_DRIVEN
RouterOpts.base_cost_type: DELAY_NORMALIZED_LENGTH
RouterOpts.fixed_channel_width: 20
RouterOpts.check_route: FULL
RouterOpts.acc_fac: 1.000000
RouterOpts.bb_factor: 3
RouterOpts.bend_cost: 0.000000
RouterOpts.first_iter_pres_fac: 0.000000
RouterOpts.initial_pres_fac: 0.500000
RouterOpts.pres_fac_mult: 1.300000
RouterOpts.max_pres_fac: 1000.000000
RouterOpts.max_router_iterations: 50
RouterOpts.min_incremental_reroute_fanout: 16
RouterOpts.initial_acc_cost_chan_congestion_threshold: 0.500000
RouterOpts.initial_acc_cost_chan_congestion_weight: 0.500000
RouterOpts.do_check_rr_graph: true
RouterOpts.verify_binary_search: false
RouterOpts.min_channel_width_hint: 0
RouterOpts.read_rr_edge_metadata: false
RouterOpts.exit_after_first_routing_iteration: false
RouterOpts.astar_fac: 1.200000
RouterOpts.astar_offset: 0.000000
RouterOpts.router_profiler_astar_fac: 1.200000
RouterOpts.enable_parallel_connection_router: false
RouterOpts.post_target_prune_fac: 1.200000
RouterOpts.post_target_prune_offset: 0
RouterOpts.multi_queue_num_threads: 1
RouterOpts.multi_queue_num_queues: 2
RouterOpts.multi_queue_direct_draining: false
RouterOpts.criticality_exp: 1.000000
RouterOpts.max_criticality: 0.990000
RouterOpts.init_wirelength_abort_threshold: 0.850000
RouterOpts.incr_reroute_delay_ripup: AUTO
RouterOpts.save_routing_per_iteration: false
RouterOpts.congested_routing_iteration_threshold_frac: 1.000000
RouterOpts.high_fanout_threshold: 64
RouterOpts.router_debug_net: -2
RouterOpts.router_debug_sink_rr: -2
RouterOpts.router_debug_iteration: -2
RouterOpts.max_convergence_count: 1
RouterOpts.reconvergence_cpd_threshold: 0.990000
RouterOpts.update_lower_bound_delays: true
RouterOpts.first_iteration_timing_report_file: 
RouterOpts.route_bb_update: DYNAMIC
RouterOpts.lookahead_type: MAP
RouterOpts.initial_timing: LOOKAHEAD
RouterOpts.router_heap: FOUR_ARY_HEAP
RouterOpts.routing_failure_predictor = SAFE
RouterOpts.routing_budgets_algorithm = DISABLE

AnalysisOpts.gen_post_synthesis_netlist: false
AnalysisOpts.gen_post_implementation_merged_netlist: false
AnalysisOpts.gen_post_implementation_sdc: false
AnalysisOpts.timing_report_npaths: 100
AnalysisOpts.timing_report_skew: false
AnalysisOpts.echo_dot_timing_graph_node: -1
AnalysisOpts.timing_report_detail: NETLIST
AnalysisOpts.post_synth_netlist_unconn_input_handling: UNCONNECTED
AnalysisOpts.post_synth_netlist_unconn_output_handling: UNCONNECTED
AnalysisOpts.post_synth_netlist_module_parameters: on

# Building complex block graph
# Building complex block graph took 0.01 seconds (max_rss 22.5 MiB, delta_rss +1.1 MiB)
Circuit file: mult4.blif
# Load circuit
# Load circuit took 0.00 seconds (max_rss 24.0 MiB, delta_rss +1.4 MiB)
# Clean circuit
Absorbed 0 LUT buffers
Inferred    0 additional primitive pins as constant generators since they have no combinationally connected inputs
Inferred    0 additional primitive pins as constant generators due to constant inputs
Swept input(s)      : 0
Swept output(s)     : 0 (0 dangling, 0 constant)
Swept net(s)        : 0
Swept block(s)      : 0
Constant Pins Marked: 0
# Clean circuit took 0.00 seconds (max_rss 24.0 MiB, delta_rss +0.0 MiB)
# Compress circuit
# Compress circuit took 0.00 seconds (max_rss 24.0 MiB, delta_rss +0.0 MiB)
# Verify circuit
# Verify circuit took 0.00 seconds (max_rss 24.0 MiB, delta_rss +0.0 MiB)
Circuit Statistics:
  Blocks: 37
    .input :       8
    .names :      21
        2-LUT:       3
        3-LUT:       1
        4-LUT:       4
        5-LUT:       3
        6-LUT:      10
    .output:       8
  Nets  : 29
    Avg Fanout:     3.7
    Max Fanout:     9.0
    Min Fanout:     1.0
  Netlist Clocks: 0
# Build Timing Graph
  Timing Graph Nodes: 137
  Timing Graph Edges: 208
  Timing Graph Levels: 8
# Build Timing Graph took 0.00 seconds (max_rss 24.2 MiB, delta_rss +0.0 MiB)
Netlist contains 0 clocks
# Load Timing Constraints

SDC file 'mult4.sdc' not found
Setting default timing constraints:
   * constrain all primary inputs and primary outputs on a virtual external clock 'virtual_io_clock'
   * optimize virtual clock to run as fast as possible
Timing constraints created 1 clocks
  Constrained Clock 'virtual_io_clock' (Virtual Clock)

# Load Timing Constraints took 0.00 seconds (max_rss 24.2 MiB, delta_rss +0.0 MiB)
# Packing
## Prepacker
## Prepacker took 0.00 seconds (max_rss 24.7 MiB, delta_rss +0.0 MiB)
## Initializing Pre-Cluster Timing
Using inter-cluster delay: 1.33777e-09
## Initializing Pre-Cluster Timing took 0.00 seconds (max_rss 25.5 MiB, delta_rss +0.8 MiB)
Begin packing 'mult4.blif'.

After removing unused inputs...
	total blocks: 37, total nets: 29, total inputs: 8, total outputs: 8
Packing with pin utilization targets: io:1,1 clb:0.8,0.6
Packing with high fanout thresholds: io:128 clb:32
Starting Clustering - Clustering Progress: 
-------------------   --------------------------   ---------
Molecules processed   Number of clusters created   FPGA size
-------------------   --------------------------   ---------
    14/37       37%                            1     4 x 4     
    21/37       56%                            2     4 x 4     
    22/37       59%                            3     4 x 4     
    23/37       62%                            4     4 x 4     
    24/37       64%                            5     4 x 4     
    25/37       67%                            6     4 x 4     
    26/37       70%                            7     4 x 4     
    27/37       72%                            8     4 x 4     
    28/37       75%                            9     4 x 4     
    29/37       78%                           10     4 x 4     
    30/37       81%                           11     4 x 4     
    31/37       83%                           12     4 x 4     
    32/37       86%                           13     4 x 4     
    33/37       89%                           14     4 x 4     
    34/37       91%                           15     4 x 4     
    35/37       94%                           16     4 x 4     
    36/37       97%                           17     4 x 4     
    37/37      100%                           18     4 x 4     

Logic Element (fle) detailed count:
  Total number of Logic Elements used : 17
  LEs used for logic and registers    : 0
  LEs used for logic only             : 17
  LEs used for registers only         : 0

FPGA sized to 4 x 4 (2x2)
Device Utilization: 0.25 (target 1.00)
	Block Utilization: 0.25 Type: io
	Block Utilization: 0.50 Type: clb

Final Clustering Statistics: 
----------   --------   ------------------------------------   --------------------------
Block Type   # Blocks   Avg. # of input clocks and pins used   Avg. # of output pins used
----------   --------   ------------------------------------   --------------------------
     EMPTY          0                                      0                            0   
        io         16                                    0.5                          0.5   
       clb          2                                     13                            9   
Absorbed logical nets 3 out of 29 nets, 26 nets not absorbed.

Netlist conversion complete.

Incr Slack updates 1 in 1.123e-06 sec
Full Max Req/Worst Slack updates 1 in 1.614e-06 sec
Incr Max Req/Worst Slack updates 0 in 0 sec
Incr Criticality updates 0 in 0 sec
Full Criticality updates 1 in 2.146e-06 sec
# Packing took 0.01 seconds (max_rss 25.8 MiB, delta_rss +1.1 MiB)
# Load packing
## Loading packed FPGA netlist file.
Netlist generated from file 'mult4.net'.
Detected 0 constant generators (to see names run with higher pack verbosity)
## Loading packed FPGA netlist file. took 0.00 seconds (max_rss 26.1 MiB, delta_rss +0.3 MiB)
Warning 6: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
Completed clustering consistency check successfully.
Cluster level netlist and block usage statistics
Netlist num_nets: 26
Netlist num_blocks: 18
Netlist EMPTY blocks: 0.
Netlist io blocks: 16.
Netlist clb blocks: 2.
Netlist inputs pins: 8
Netlist output pins: 8

Pb types usage...
  io             : 16
   inpad         : 8
   outpad        : 8
  clb            : 2
   fle           : 17
    lut5inter    : 7
     ble5        : 11
      lut5       : 11
       lut       : 11
    ble6         : 10
     lut6        : 10
      lut        : 10

# Load packing took 0.03 seconds (max_rss 64.4 MiB, delta_rss +38.6 MiB)
# Create Device
## Build Device Grid
FPGA sized to 4 x 4: 16 grid tiles (2x2)
## Build Device Grid took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph
X-direction routing channel width is 20
Y-direction routing channel width is 20
### Build RR Graph Edges
### Build RR Graph Edges took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
  RR Graph Nodes: 744
  RR Graph Edges: 1732
# Create Device took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Resource usage...
	Netlist
		16	blocks of type: io
	Architecture
		64	blocks of type: io
	Netlist
		2	blocks of type: clb
	Architecture
		4	blocks of type: clb

Device Utilization: 0.25 (target 1.00)
	Physical Tile io:
	Block Utilization: 0.25 Logical Block: io
	Physical Tile clb:
	Block Utilization: 0.50 Logical Block: clb


# Computing router lookahead map
## Computing wire lookahead
## Computing wire lookahead took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
## Computing src/opin lookahead
## Computing src/opin lookahead took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Computing router lookahead map took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Compressed grid construction
# Compressed grid construction took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Bounding box mode is Cube

# Computing placement delta delay look-up
RR graph channel widths unchanged, skipping RR graph rebuild
Serial Connection Router is being destroyed. Time spent on path search: 0.000 seconds.
# Computing placement delta delay look-up took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Placement
## Initial Placement
Initial placement iteration 0 has finished successfully
## Initial Placement took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Using simple RL 'Softmax agent' for choosing move and block types

Completed placement consistency check successfully.
Initial placement cost: 1 bb_cost: 5.30935 td_cost: 6.47339e-09
Initial placement BB estimate of wirelength: 98
Initial placement estimated Critical Path Delay (CPD): 2.07439 ns
Initial placement estimated setup Total Negative Slack (sTNS): -11.6502 ns
Initial placement estimated setup Worst Negative Slack (sWNS): -2.07439 ns

Initial placement estimated setup slack histogram:
[ -2.1e-09:   -2e-09) 1 ( 12.5%) |****************
[   -2e-09: -1.8e-09) 0 (  0.0%) |
[ -1.8e-09: -1.7e-09) 2 ( 25.0%) |*********************************
[ -1.7e-09: -1.6e-09) 0 (  0.0%) |
[ -1.6e-09: -1.5e-09) 2 ( 25.0%) |*********************************
[ -1.5e-09: -1.4e-09) 0 (  0.0%) |
[ -1.4e-09: -1.2e-09) 0 (  0.0%) |
[ -1.2e-09: -1.1e-09) 0 (  0.0%) |
[ -1.1e-09:   -1e-09) 0 (  0.0%) |
[   -1e-09: -8.9e-10) 3 ( 37.5%) |*************************************************
Placement contains 0 placement macros involving 0 blocks (average macro size -nan)

Moves per temperature: 23

---- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
Tnum   Time       T Av Cost Av BB Cost Av TD Cost     CPD       sTNS     sWNS Ac Rate Std Dev  R lim Crit Exp Tot Moves  Alpha
      (sec)                                          (ns)       (ns)     (ns)                                                 
---- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
   1    0.0 6.1e-03   0.999       5.14 6.4215e-09   2.074      -11.7   -2.074   0.696  0.0061    3.0     1.00        23  1.000
   2    0.0 5.8e-03   0.997       5.05 6.3206e-09   2.074      -11.3   -2.074   0.696  0.0051    3.0     1.00        46  0.950
   3    0.0 5.5e-03   1.012       5.15 6.34e-09     2.074      -11.3   -2.074   0.478  0.0081    3.0     1.00        69  0.950
   4    0.0 5.3e-03   0.981       5.10 6.3132e-09   2.098      -11.6   -2.098   0.522  0.0035    3.0     1.00        92  0.950
   5    0.0 5.0e-03   0.992       4.93 6.3449e-09   2.074      -11.3   -2.074   0.261  0.0045    3.0     1.00       115  0.950
   6    0.0 4.7e-03   0.984       4.80 4.9649e-09   2.074      -11.3   -2.074   0.304  0.0038    2.5     2.88       138  0.950
   7    0.0 4.5e-03   1.014       4.85 4.5973e-09   2.074      -11.6   -2.074   0.565  0.0105    2.1     4.05       161  0.950
   8    0.0 4.3e-03   1.005       5.01 5.0687e-09   2.098      -11.7   -2.098   0.391  0.0077    2.4     3.12       184  0.950
   9    0.0 4.1e-03   0.989       5.00 4.5274e-09   2.169      -11.8   -2.169   0.522  0.0109    2.3     3.53       207  0.950
  10    0.0 3.9e-03   0.979       4.79 4.6982e-09   2.169      -11.8   -2.169   0.391  0.0090    2.5     2.87       230  0.950
  11    0.0 3.7e-03   1.011       4.88 4.7736e-09   2.074      -11.3   -2.074   0.348  0.0068    2.3     3.29       253  0.950
  12    0.0 3.5e-03   0.996       4.92 4.4879e-09   2.074      -11.3   -2.074   0.435  0.0055    2.1     4.05       276  0.950
  13    0.0 3.3e-03   0.999       4.82 4.4713e-09   2.074      -11.3   -2.074   0.348  0.0002    2.1     4.09       299  0.950
  14    0.0 3.1e-03   0.997       4.80 4.2635e-09   2.074      -11.3   -2.074   0.348  0.0031    1.9     4.77       322  0.950
  15    0.0 3.0e-03   1.006       4.90 4.1033e-09   2.074      -11.3   -2.074   0.522  0.0041    1.7     5.39       345  0.950
  16    0.0 2.8e-03   0.997       4.90 4.2303e-09   2.074      -11.3   -2.074   0.261  0.0014    1.9     4.89       368  0.950
  17    0.0 2.7e-03   0.999       4.91 3.9513e-09   2.074      -11.3   -2.074   0.478  0.0027    1.5     6.08       391  0.950
  18    0.0 2.6e-03   0.992       4.81 3.995e-09    2.074      -11.3   -2.074   0.478  0.0050    1.6     5.87       414  0.950
  19    0.0 2.4e-03   1.002       4.78 4.0425e-09   2.074      -11.3   -2.074   0.261  0.0031    1.7     5.65       437  0.950
  20    0.0 2.3e-03   1.002       4.86 3.8312e-09   2.074      -11.3   -2.074   0.391  0.0034    1.4     6.70       460  0.950
  21    0.0 2.2e-03   0.997       4.85 3.7898e-09   2.074      -11.3   -2.074   0.348  0.0045    1.3     6.93       483  0.950
  22    0.0 2.1e-03   0.990       4.74 3.7203e-09   2.074      -11.3   -2.074   0.304  0.0044    1.2     7.36       506  0.950
  23    0.0 2.0e-03   0.999       4.69 3.6359e-09   2.074      -11.3   -2.074   0.174  0.0014    1.0     7.92       529  0.950
  24    0.0 1.9e-03   1.004       4.70 3.6242e-09   2.074      -11.3   -2.074   0.391  0.0024    1.0     8.00       552  0.950
  25    0.0 1.8e-03   1.000       4.72 3.6242e-09   2.074      -11.3   -2.074   0.304  0.0000    1.0     8.00       575  0.950
  26    0.0 1.7e-03   1.000       4.72 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0000    1.0     8.00       598  0.950
  27    0.0 1.6e-03   0.998       4.70 3.6242e-09   2.074      -11.3   -2.074   0.435  0.0011    1.0     8.00       621  0.950
  28    0.0 1.5e-03   1.005       4.77 3.6242e-09   2.074      -11.3   -2.074   0.130  0.0029    1.0     8.00       644  0.950
Agent's 2nd state: 
  29    0.0 1.2e-03   0.998       4.74 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0038    1.0     8.00       667  0.800
Checkpoint saved: bb_costs=4.68206, TD costs=3.62421e-09, CPD=  2.074 (ns) 
  30    0.0 1.2e-03   1.000       4.68 3.6242e-09   2.074      -11.3   -2.074   0.304  0.0011    1.0     8.00       690  0.950
  31    0.0 1.1e-03   1.000       4.66 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0000    1.0     8.00       713  0.950
  32    0.0 1.1e-03   1.000       4.66 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       736  0.950
  33    0.0 8.4e-04   1.000       4.66 3.6242e-09   2.074      -11.3   -2.074   0.043  0.0000    1.0     8.00       759  0.800
  34    0.0 6.7e-04   0.998       4.64 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0014    1.0     8.00       782  0.800
  35    0.0 6.4e-04   1.000       4.65 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       805  0.950
  36    0.0 5.1e-04   1.000       4.65 3.6242e-09   2.074      -11.3   -2.074   0.217  0.0011    1.0     8.00       828  0.800
  37    0.0 4.9e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0003    1.0     8.00       851  0.950
  38    0.0 4.6e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       874  0.950
  39    0.0 3.7e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0000    1.0     8.00       897  0.800
  40    0.0 3.5e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       920  0.950
  41    0.0 2.8e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.130  0.0000    1.0     8.00       943  0.800
  42    0.0 2.2e-04   0.997       4.60 3.6242e-09   2.074      -11.3   -2.074   0.217  0.0000    1.0     8.00       966  0.800
  43    0.0 2.1e-04   1.000       4.60 3.6242e-09   2.074      -11.3   -2.074   0.043  0.0000    1.0     8.00       989  0.950
  44    0.0 0.0e+00   1.000       4.60 3.6242e-09   2.074      -11.3   -2.074   0.130  0.0000    1.0     8.00      1012  0.800
## Placement Quench took 0.00 seconds (max_rss 64.4 MiB)
post-quench CPD = 2.07439 (ns) 

Completed placement consistency check successfully.

Swaps called: 1030

Aborted Move Reasons:
  No moves aborted

BB estimate of min-dist (placement) wire length: 86

Placement estimated critical path delay (least slack): 2.07439 ns, Fmax: 482.069 MHz
Placement estimated setup Worst Negative Slack (sWNS): -2.07439 ns
Placement estimated setup Total Negative Slack (sTNS): -11.3066 ns

Placement estimated setup slack histogram:
[ -2.1e-09:   -2e-09) 1 ( 12.5%) |****************
[   -2e-09: -1.8e-09) 0 (  0.0%) |
[ -1.8e-09: -1.7e-09) 2 ( 25.0%) |*********************************
[ -1.7e-09: -1.6e-09) 0 (  0.0%) |
[ -1.6e-09: -1.5e-09) 2 ( 25.0%) |*********************************
[ -1.5e-09: -1.3e-09) 0 (  0.0%) |
[ -1.3e-09: -1.2e-09) 0 (  0.0%) |
[ -1.2e-09: -1.1e-09) 0 (  0.0%) |
[ -1.1e-09: -9.8e-10) 0 (  0.0%) |
[ -9.8e-10: -8.6e-10) 3 ( 37.5%) |*************************************************

Placement estimated geomean non-virtual intra-domain period: nan ns (nan MHz)
Placement estimated fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz)

Placement cost: 1, bb_cost: 4.5957, td_cost: 3.62421e-09, 

Placement resource usage:
  io  implemented as io : 16
  clb implemented as clb: 2

Placement number of temperatures: 44
Placement total # of swap attempts: 1030
	Swaps accepted:  311 (30.2 %)
	Swaps rejected:  719 (69.8 %)
	Swaps aborted:    0 ( 0.0 %)


Placement perturbation distribution by block and move type: 
------------------ ----------------- ---------------- ---------------- --------------- ------------ 
    Block Type         Move Type       (%) of Total      Accepted(%)     Rejected(%)    Aborted(%)
------------------ ----------------- ---------------- ---------------- --------------- ------------ 
io                 Uniform                24.08            35.48           64.52          0.00         
                   Median                 17.86            28.80           71.20          0.00         
                   Centroid               16.60            39.18           60.82          0.00         
                   W. Centroid            21.07            38.71           61.29          0.00         
                   W. Median              3.40             11.43           88.57          0.00         
                   Crit. Uniform          1.84             21.05           78.95          0.00         
                   Feasible Region        2.62             37.04           62.96          0.00         

clb                Uniform                2.04             0.00            100.00         0.00         
                   Median                 1.17             8.33            91.67          0.00         
                   Centroid               2.04             0.00            100.00         0.00         
                   W. Centroid            1.75             0.00            100.00         0.00         
                   W. Median              0.78             0.00            100.00         0.00         
                   Crit. Uniform          1.84             0.00            100.00         0.00         
                   Feasible Region        2.91             0.00            100.00         0.00         


Placement Quench timing analysis took 3.4351e-05 seconds (3.1387e-05 STA, 2.964e-06 slack) (1 full updates: 1 setup, 0 hold, 0 combined).
Placement Total  timing analysis took 0.00170863 seconds (0.00154666 STA, 0.000161969 slack) (46 full updates: 46 setup, 0 hold, 0 combined).
update_td_costs: connections 0 nets 0 sum_nets 0 total 0
# Placement took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

# Routing
RR graph channel widths unchanged, skipping RR graph rebuild
## Initializing router criticalities
Initial Net Connection Criticality Histogram:
[        0:      0.1)  0 (  0.0%) |
[      0.1:      0.2)  0 (  0.0%) |
[      0.2:      0.3)  0 (  0.0%) |
[      0.3:      0.4)  0 (  0.0%) |
[      0.4:      0.5)  5 ( 14.7%) |********************
[      0.5:      0.6)  0 (  0.0%) |
[      0.6:      0.7)  0 (  0.0%) |
[      0.7:      0.8)  7 ( 20.6%) |****************************
[      0.8:      0.9) 10 ( 29.4%) |****************************************
[      0.9:        1) 12 ( 35.3%) |************************************************
## Initializing router criticalities took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
Iter   Time    pres  BBs    Heap  Re-Rtd  Re-Rtd Overused RR Nodes      Wirelength      CPD       sTNS       sWNS       hTNS       hWNS Est Succ
      (sec)     fac Updt    push    Nets   Conns                                       (ns)       (ns)       (ns)       (ns)       (ns)     Iter
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
   1    0.0     0.0    0     622      26      34      25 ( 3.360%)     103 (42.9%)    2.473     -13.88     -2.473      0.000      0.000      N/A
Incr Slack updates 46 in 3.2827e-05 sec
Full Max Req/Worst Slack updates 3 in 8.825e-06 sec
Incr Max Req/Worst Slack updates 43 in 1.9546e-05 sec
Incr Criticality updates 40 in 6.8983e-05 sec
Full Criticality updates 6 in 1.1883e-05 sec
   2    0.0     0.5    0     514      20      27      17 ( 2.285%)     102 (42.5%)    2.473     -13.82     -2.473      0.000      0.000      N/A
   3    0.0     0.6    0     455      13      17      19 ( 2.554%)     110 (45.8%)    2.473     -14.19     -2.473      0.000      0.000      N/A
   4    0.0     0.8    0     472      14      19      15 ( 2.016%)     110 (45.8%)    2.473     -14.18     -2.473      0.000      0.000      N/A
   5    0.0     1.1    0     471      13      18      13 ( 1.747%)     116 (48.3%)    2.473     -14.42     -2.473      0.000      0.000      N/A
   6    0.0     1.4    0     354      13      19      13 ( 1.747%)     120 (50.0%)    2.473     -14.50     -2.473      0.000      0.000      N/A
   7    0.0     1.9    0     430      13      19      11 ( 1.478%)     121 (50.4%)    2.473     -14.63     -2.473      0.000      0.000      N/A
   8    0.0     2.4    0     380      12      17      10 ( 1.344%)     115 (47.9%)    2.473     -14.38     -2.473      0.000      0.000      N/A
   9    0.0     3.1    0     275       9      13       3 ( 0.403%)     128 (53.3%)    2.471     -15.09     -2.471      0.000      0.000      N/A
  10    0.0     4.1    0     209       5       7       2 ( 0.269%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       14
  11    0.0     5.3    0     192       5       7       3 ( 0.403%)     129 (53.8%)    2.471     -15.25     -2.471      0.000      0.000       12
  12    0.0     6.9    0     176       4       6       2 ( 0.269%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       13
  13    0.0     9.0    0     246       6       8       3 ( 0.403%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       13
  14    0.0    11.6    0     197       4       5       3 ( 0.403%)     122 (50.8%)    2.471     -14.85     -2.471      0.000      0.000       15
  15    0.0    15.1    0     173       3       4       2 ( 0.269%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       20
  16    0.0    19.7    0     388       6       8       4 ( 0.538%)     147 (61.2%)    2.471     -16.00     -2.471      0.000      0.000       20
  17    0.0    25.6    0     153       5       6       2 ( 0.269%)     133 (55.4%)    2.526     -15.50     -2.526      0.000      0.000      inf
  18    0.0    33.3    0     106       5       7       1 ( 0.134%)     137 (57.1%)    2.645     -15.62     -2.645      0.000      0.000      inf
  19    0.0    43.3    0     108       5       7       2 ( 0.269%)     133 (55.4%)    2.663     -15.63     -2.663      0.000      0.000       31
  20    0.0    56.2    0     108       4       6       1 ( 0.134%)     133 (55.4%)    2.529     -15.51     -2.529      0.000      0.000       33
  21    0.0    73.1    0     219       5       7       2 ( 0.269%)     138 (57.5%)    2.529     -15.83     -2.529      0.000      0.000       23
  22    0.0    95.0    0      84       3       5       1 ( 0.134%)     133 (55.4%)    2.529     -15.51     -2.529      0.000      0.000       26
  23    0.0   123.5    0     128       4       6       1 ( 0.134%)     134 (55.8%)    2.665     -15.64     -2.665      0.000      0.000       24
  24    0.0   160.6    0     148       4       6       1 ( 0.134%)     134 (55.8%)    2.665     -15.64     -2.665      0.000      0.000       24
  25    0.0   208.8    0     146       4       6       3 ( 0.403%)     139 (57.9%)    2.935     -15.91     -2.935      0.000      0.000       23
  26    0.0   271.4    0     112       4       6       1 ( 0.134%)     133 (55.4%)    2.529     -15.51     -2.529      0.000      0.000       27
  27    0.0   352.8    0     213       5       7       2 ( 0.269%)     141 (58.7%)    3.031     -16.01     -3.031      0.000      0.000       27
  28    0.0   458.7    0     181       4       6       1 ( 0.134%)     134 (55.8%)    2.665     -15.64     -2.665      0.000      0.000       31
  29    0.0   596.3    0     140       4       6       2 ( 0.269%)     142 (59.2%)    3.165     -16.14     -3.165      0.000      0.000       31
  30    0.0   775.1    0     133       4       6       3 ( 0.403%)     143 (59.6%)    3.165     -16.30     -3.165      0.000      0.000       38
  31    0.0  1000.0    0     192       6       9       2 ( 0.269%)     151 (62.9%)    2.935     -16.69     -2.935      0.000      0.000      132
  32    0.0  1000.0    0     196       6       8       3 ( 0.403%)     152 (63.3%)    3.009     -16.97     -3.009      0.000      0.000      inf
  33    0.0  1000.0    0     204       5       7       1 ( 0.134%)     141 (58.7%)    2.935     -16.15     -2.935      0.000      0.000       12
  34    0.0  1000.0    0     210       5       7       0 ( 0.000%)     145 (60.4%)    2.935     -16.34     -2.935      0.000      0.000        5
Restoring best routing
Critical path: 2.93509 ns
Successfully routed after 34 routing iterations.
Final Net Connection Criticality Histogram:
[        0:      0.1)  0 (  0.0%) |
[      0.1:      0.2)  0 (  0.0%) |
[      0.2:      0.3)  0 (  0.0%) |
[      0.3:      0.4)  1 (  2.9%) |***
[      0.4:      0.5)  2 (  5.9%) |******
[      0.5:      0.6)  3 (  8.8%) |*********
[      0.6:      0.7)  1 (  2.9%) |***
[      0.7:      0.8)  5 ( 14.7%) |***************
[      0.8:      0.9)  6 ( 17.6%) |******************
[      0.9:        1) 16 ( 47.1%) |************************************************
Router Stats: total_nets_routed: 248 total_connections_routed: 346 total_heap_pushes: 8335 total_heap_pops: 5679 
Serial Connection Router is being destroyed. Time spent on path search: 0.000 seconds.
# Routing took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Checking to ensure routing is legal...
# Checking to ensure non-configurable edges are legal
# Checking to ensure non-configurable edges are legal took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Completed routing consistency check successfully.

Serial number (magic cookie) for the routing is: -1300952
Circuit successfully routed with a channel width factor of 20.
# Synchronize the packed netlist to routing optimization
## Annotating rr_node with routed nets
## Annotating rr_node with routed nets took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Found 37 mismatches between routing and packing results.
Fixed 26 routing traces due to mismatch between routing and packing results.
# Synchronize the packed netlist to routing optimization took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Final Clustering Statistics: 
----------   --------   ------------------------------------   --------------------------
Block Type   # Blocks   Avg. # of input clocks and pins used   Avg. # of output pins used
----------   --------   ------------------------------------   --------------------------
     EMPTY          0                                      0                            0   
        io         16                                    0.5                          0.5   
       clb          2                                     13                            9   
Absorbed logical nets 3 out of 29 nets, 26 nets not absorbed.


Average number of bends per net: 2.50000  Maximum # of bends: 14

Number of global nets: 0
Number of routed nets (nonglobal): 26
Wire length results (in units of 1 clb segments)...
	Total wirelength: 145, average net length: 5.57692
	Maximum net length: 23

Wire length results in terms of physical segments...
	Total wiring segments used: 94, average wire segments per net: 3.61538
	Maximum segments used by a net: 15
	Total local nets with reserved CLB opins: 0
Total number of nets absorbed: 0

Routing channel utilization histogram:
[        1:      inf) 0 (  0.0%) |
[      0.9:        1) 0 (  0.0%) |
[      0.8:      0.9) 0 (  0.0%) |
[      0.7:      0.8) 5 ( 27.8%) |*****************************************
[      0.5:      0.6) 6 ( 33.3%) |*************************************************
[      0.4:      0.5) 0 (  0.0%) |
[      0.3:      0.4) 1 (  5.6%) |********
[      0.2:      0.3) 0 (  0.0%) |
[      0.1:      0.2) 0 (  0.0%) |
[        0:      0.1) 6 ( 33.3%) |*************************************************
Maximum routing channel utilization:      0.75 at (2,0)

X - Directed channels: layer   y   max occ   ave occ   ave cap
                        ----- ---- -------- -------- --------
                            0    0       15   13.500       20
                            0    1       13   13.000       20
                            0    2       13   12.500       20
Y - Directed channels: layer   x   max occ   ave occ   ave cap
                        ----- ---- -------- -------- --------
                            0    0       12   11.500       20
                            0    1       11    9.500       20
                            0    2       13   12.500       20

Total existing wires segments: CHANX 78, CHANY 67, ALL 145
Total used wires segments:     CHANX 78, CHANY 67, ALL 145
Usage percentage:               CHANX 0%, CHANY -1%, ALL -1554953993%

Logic area (in minimum width transistor areas, excludes I/Os and empty grid tiles)...
	Total logic block area (Warning, need to add pitch of routing to blocks with height > 3): 215576
	Total used logic block area: 107788

Routing area (in minimum width transistor areas)...
	Total routing area: 12917.9, per logic tile: 807.366

Total Number of Wiring Segments by Direction: direction length number
                                              --------- ------ -------
                                                      X      4     78
                                                      Y      4     78

X - Directed Wiring Segment usage by length: length utilization
                                             ------ -----------
                                             4       0.628

Y - Directed Wiring Segment usage by length: length utilization
                                             ------ -----------
                                             4       0.577

Segment occupancy by length: Length Occupancy Capacity Utilization
                             ------ --------- -------- -----------
                             L4            94      156       0.603

Segment occupancy by type: name type utilization
                           ---- ---- -----------
                             L4    0       0.603

Final hold Worst Negative Slack (hWNS): 0 ns
Final hold Total Negative Slack (hTNS): 0 ns

Final hold slack histogram:
[  8.3e-10:  9.5e-10) 3 ( 37.5%) |*************************************************
[  9.5e-10:  1.1e-09) 1 ( 12.5%) |****************
[  1.1e-09:  1.2e-09) 1 ( 12.5%) |****************
[  1.2e-09:  1.3e-09) 0 (  0.0%) |
[  1.3e-09:  1.4e-09) 2 ( 25.0%) |*********************************
[  1.4e-09:  1.5e-09) 0 (  0.0%) |
[  1.5e-09:  1.7e-09) 0 (  0.0%) |
[  1.7e-09:  1.8e-09) 0 (  0.0%) |
[  1.8e-09:  1.9e-09) 0 (  0.0%) |
[  1.9e-09:    2e-09) 1 ( 12.5%) |****************

Final critical path delay (least slack): 2.93509 ns, Fmax: 340.705 MHz
Final setup Worst Negative Slack (sWNS): -2.93509 ns
Final setup Total Negative Slack (sTNS): -16.3447 ns

Final setup slack histogram:
[ -2.9e-09: -2.8e-09) 1 ( 12.5%) |*************************
[ -2.8e-09: -2.6e-09) 1 ( 12.5%) |*************************
[ -2.6e-09: -2.4e-09) 0 (  0.0%) |
[ -2.4e-09: -2.3e-09) 1 ( 12.5%) |*************************
[ -2.3e-09: -2.1e-09) 0 (  0.0%) |
[ -2.1e-09: -1.9e-09) 2 ( 25.0%) |*************************************************
[ -1.9e-09: -1.8e-09) 0 (  0.0%) |
[ -1.8e-09: -1.6e-09) 1 ( 12.5%) |*************************
[ -1.6e-09: -1.4e-09) 0 (  0.0%) |
[ -1.4e-09: -1.3e-09) 2 ( 25.0%) |*************************************************

Final geomean non-virtual intra-domain period: nan ns (nan MHz)
Final fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz)

Incr Slack updates 1 in 4.573e-06 sec
Full Max Req/Worst Slack updates 1 in 9.49e-07 sec
Incr Max Req/Worst Slack updates 0 in 0 sec
Incr Criticality updates 0 in 0 sec
Full Criticality updates 1 in 2.288e-06 sec
Flow timing analysis took 0.00439292 seconds (0.00387641 STA, 0.000516512 slack) (83 full updates: 47 setup, 0 hold, 36 combined).
VPR succeeded
The entire flow of VPR took 0.06 seconds (max_rss 64.4 MiB)

Command line to execute: read_openfpga_arch -f /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run026/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_40nm_openfpga.xml

Confirm selected options when call command 'read_openfpga_arch':
--file, -f: /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run026/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_40nm_openfpga.xml
Reading XML architecture '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run026/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_40nm_openfpga.xml'...
Read OpenFPGA architecture
Warning 7: Automatically set circuit model 'frac_lut6' to be default in its type.
Warning 8: Automatically set circuit model 'DFFSRQ' to be default in its type.
Warning 9: Automatically set circuit model 'DFFR' to be default in its type.
Warning 10: Automatically set circuit model 'GPIO' to be default in its type.
Use the default configurable memory model 'DFFR' for circuit model 'mux_2level' port 'sram')
Use the default configurable memory model 'DFFR' for circuit model 'mux_2level_tapbuf' port 'sram')
Use the default configurable memory model 'DFFR' for circuit model 'mux_1level_tapbuf' port 'sram')
Use the default configurable memory model 'DFFR' for circuit model 'frac_lut6' port 'sram')
Read OpenFPGA architecture took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Check circuit library
Checking circuit library passed.
Check circuit library took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Found 0 errors when checking configurable memory circuit models!
Found 0 errors when checking configuration protocol!
Found 0 errors when checking tile annotation!

Command line to execute: read_openfpga_simulation_setting -f /home/moshida/OpenFPGA/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml

Confirm selected options when call command 'read_openfpga_simulation_setting':
--file, -f: /home/moshida/OpenFPGA/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Reading XML simulation setting '/home/moshida/OpenFPGA/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
Read OpenFPGA simulation settings
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: link_openfpga_arch --activity_file mult4_ace_out.act --sort_gsb_chan_node_in_edges

Confirm selected options when call command 'link_openfpga_arch':
--activity_file: mult4_ace_out.act
--sort_gsb_chan_node_in_edges: on
--verbose: off
Link OpenFPGA architecture to VPR architecture
# Build fast look-up for physical tile pins
# Build fast look-up for physical tile pins took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Building annotation for physical modes in pb_type...Done
Check physical mode annotation for pb_types passed.

Building annotation about physical types for pb_type interconnection...Done

Building annotation between operating and physical pb_types...Done
Check physical pb_type annotation for pb_types passed.

Building annotation between physical pb_types and circuit models...Done
Check physical pb_type annotation for circuit model passed.

Building annotation between physical pb_types and mode selection bits...Done
Check pb_type annotation for mode selection bits passed.
Assigning unique indices for primitive pb_graph nodes...Done
Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...Done
Check pb_graph annotation for physical nodes and pins passed.
Binded 2 routing resource graph switches to circuit models
Binded 1 routing segments to circuit models
Binded 0 direct connections to circuit models
# Annotating rr_node with routed nets
# Annotating rr_node with routed nets took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Loaded node-to-net mapping
Annotating previous nodes for rr_node...Warning 11: Override the previous node 'IPIN:467 side: (RIGHT,) (2,2,0)' by previous node 'IPIN:466 side: (RIGHT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 12: Override the previous node 'IPIN:466 side: (RIGHT,) (2,2,0)' by previous node 'IPIN:483 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 13: Override the previous node 'IPIN:245 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:249 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 14: Override the previous node 'IPIN:483 side: (LEFT,) (2,2,0)' by previous node 'IPIN:451 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 15: Override the previous node 'IPIN:249 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:261 side: (LEFT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 16: Override the previous node 'IPIN:261 side: (LEFT,) (2,1,0)' by previous node 'IPIN:223 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 17: Override the previous node 'IPIN:451 side: (TOP,) (2,2,0)' by previous node 'IPIN:452 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 18: Override the previous node 'IPIN:452 side: (TOP,) (2,2,0)' by previous node 'IPIN:489 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 19: Override the previous node 'IPIN:223 side: (TOP,) (2,1,0)' by previous node 'IPIN:224 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 20: Override the previous node 'IPIN:489 side: (LEFT,) (2,2,0)' by previous node 'IPIN:484 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 21: Override the previous node 'IPIN:224 side: (TOP,) (2,1,0)' by previous node 'IPIN:246 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 22: Override the previous node 'IPIN:484 side: (LEFT,) (2,2,0)' by previous node 'IPIN:454 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 23: Override the previous node 'IPIN:246 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:244 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 24: Override the previous node 'IPIN:454 side: (TOP,) (2,2,0)' by previous node 'IPIN:482 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 25: Override the previous node 'IPIN:244 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:243 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 26: Override the previous node 'IPIN:482 side: (LEFT,) (2,2,0)' by previous node 'IPIN:455 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 27: Override the previous node 'IPIN:243 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:226 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 28: Override the previous node 'IPIN:226 side: (TOP,) (2,1,0)' by previous node 'IPIN:233 side: (RIGHT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 29: Override the previous node 'IPIN:233 side: (RIGHT,) (2,1,0)' by previous node 'IPIN:221 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 30: Override the previous node 'IPIN:221 side: (TOP,) (2,1,0)' by previous node 'IPIN:222 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 31: Override the previous node 'IPIN:222 side: (TOP,) (2,1,0)' by previous node 'IPIN:254 side: (LEFT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 32: Override the previous node 'IPIN:254 side: (LEFT,) (2,1,0)' by previous node 'IPIN:235 side: (RIGHT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 33: Override the previous node 'IPIN:235 side: (RIGHT,) (2,1,0)' by previous node 'IPIN:230 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 34: Override the previous node 'IPIN:230 side: (TOP,) (2,1,0)' by previous node 'IPIN:236 side: (RIGHT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Done with 0 nodes mapping
Built 1732 incoming edges for routing resource graph
# Build General Switch Block(GSB) annotation on top of routing resource graph
[11%] Backannotated GSB[0][0]
[22%] Backannotated GSB[0][1]
[33%] Backannotated GSB[0][2]
[44%] Backannotated GSB[1][0]
[55%] Backannotated GSB[1][1]
[66%] Backannotated GSB[1][2]
[77%] Backannotated GSB[2][0]
[88%] Backannotated GSB[2][1]
[100%] Backannotated GSB[2][2]
Backannotated 9 General Switch Blocks (GSBs).
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
[11%] Sorted incoming edges for each routing track output node of GSB[0][0]
[22%] Sorted incoming edges for each routing track output node of GSB[0][1]
[33%] Sorted incoming edges for each routing track output node of GSB[0][2]
[44%] Sorted incoming edges for each routing track output node of GSB[1][0]
[55%] Sorted incoming edges for each routing track output node of GSB[1][1]
[66%] Sorted incoming edges for each routing track output node of GSB[1][2]
[77%] Sorted incoming edges for each routing track output node of GSB[2][0]
[88%] Sorted incoming edges for each routing track output node of GSB[2][1]
[100%] Sorted incoming edges for each routing track output node of GSB[2][2]
Sorted incoming edges for each routing track output node of 9 General Switch Blocks (GSBs).
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each input pin node of General Switch Block(GSB)
[11%] Sorted incoming edges for each input pin node of GSB[0][0]
[22%] Sorted incoming edges for each input pin node of GSB[0][1]
[33%] Sorted incoming edges for each input pin node of GSB[0][2]
[44%] Sorted incoming edges for each input pin node of GSB[1][0]
[55%] Sorted incoming edges for each input pin node of GSB[1][1]
[66%] Sorted incoming edges for each input pin node of GSB[1][2]
[77%] Sorted incoming edges for each input pin node of GSB[2][0]
[88%] Sorted incoming edges for each input pin node of GSB[2][1]
[100%] Sorted incoming edges for each input pin node of GSB[2][2]
Sorted incoming edges for each input pin node of 9 General Switch Blocks (GSBs).
# Sort incoming edges for each input pin node of General Switch Block(GSB) took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build a library of physical multiplexers
Built a multiplexer library of 12 physical multiplexers.
Maximum multiplexer size is 64.
	model 'mux_2level_tapbuf', input_size='5'
	model 'mux_2level_tapbuf', input_size='3'
	model 'mux_2level_tapbuf', input_size='4'
	model 'mux_2level_tapbuf', input_size='10'
	model 'mux_2level_tapbuf', input_size='8'
	model 'mux_2level_tapbuf', input_size='9'
	model 'mux_2level_tapbuf', input_size='12'
	model 'mux_2level_tapbuf', input_size='11'
	model 'mux_2level_tapbuf', input_size='6'
	model 'mux_2level', input_size='61'
	model 'mux_1level_tapbuf', input_size='3'
	model 'frac_lut6', input_size='64'
# Build a library of physical multiplexers took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build the annotation about direct connection between tiles
Built 0 tile-to-tile direct connections
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Building annotation for post-routing and clustering synchornization results...Done
Building annotation for mapped blocks on grid locations...Done
User specified the operating clock frequency to use VPR results
Use VPR critical path delay 3.52211e-18 [ns] with a 20 [%] slack in OpenFPGA.
Incr Slack updates 1 in 9.228e-06 sec
Full Max Req/Worst Slack updates 1 in 2.19e-06 sec
Incr Max Req/Worst Slack updates 0 in 0 sec
Incr Criticality updates 0 in 0 sec
Full Criticality updates 1 in 9.03e-06 sec
Will apply operating clock frequency 283.921 [MHz] to simulations
User specified the number of operating clock cycles to be inferred from signal activities
Average net density: 0.08
Median net density: 0.00
Average net density after weighting: 0.13
Will apply 12 operating clock cycles to simulations
Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

Confirm selected options when call command 'check_netlist_naming_conflict':
--fix: on
--report: ./netlist_renaming.xml
Check naming violations of netlist blocks and nets
Fixed 66 naming conflicts in the netlist.
Naming fix-up report is generated to file './netlist_renaming.xml'
Check naming violations of netlist blocks and nets took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: build_fabric --compress_routing

Confirm selected options when call command 'build_fabric':
--frame_view: off
--compress_routing: on
--duplicate_grid_pin: off
--name_module_using_index: off
--load_fabric_key: off
--write_fabric_key: off
--group_tile: off
--group_config_block: off
--generate_random_fabric_key: off
--verbose: off
Identify unique General Switch Blocks (GSBs)
Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%)
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)


Build fabric module graph
# Build constant generator modules
# Build constant generator modules took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build user-defined modules
# Build user-defined modules took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build essential (inverter/buffer/logic gate) modules
# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build local encoder (for multiplexers) modules
# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Building multiplexer modules
# Building multiplexer modules took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build Look-Up Table (LUT) modules
# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build wire modules
# Build wire modules took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build memory modules
# Build memory modules took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build grid modules
Building logical tiles...Done
Building physical tiles...Done
# Build grid modules took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build unique routing modules...
# Build unique routing modules... took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build FPGA fabric module
## Add grid instances to top module
## Add grid instances to top module took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
## Add switch block instances to top module
## Add switch block instances to top module took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
## Add module nets between grids and GSBs
## Add module nets between grids and GSBs took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
## Add module nets for inter-tile connections
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
## Build configurable regions for the top module
## Build configurable regions for the top module took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
## Add module nets for configuration buses
## Add module nets for configuration buses took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
# Build FPGA fabric module took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Build fabric module graph took 0.01 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Create I/O location mapping for top module
Create I/O location mapping for top module took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Create global port info for top module
Create global port info for top module took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: repack --verbose

Confirm selected options when call command 'repack':
--design_constraints: off
--ignore_global_nets_on_pins: off
--verbose: on
Build routing resource graph for the physical implementation of logical tile
Building routing resource graph for logical tile 'io'...
	Number of nodes: 8
	Number of edges: 7
Check routing resource graph for logical tile passed
Building routing resource graph for logical tile 'clb'...
	Number of nodes: 574
	Number of edges: 4153
Check routing resource graph for logical tile passed
Done
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Repack clustered blocks to physical implementation of logical tile
Repack clustered block 'new_$abc$328$new_n22'...
Follow the same mapping results for net 'B[2]' on pin 'I[0]' during repacking (constrained net name is )
Pb route for Net B[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[0] -> clb[0].I[0]
Sink nodes:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[4]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[1]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[1]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[2]' during repacking (constrained net name is )
Follow the same mapping results for net 'new_$abc$328$new_n25' on pin 'I[3]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n25:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[3] -> clb[0].I[3]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[3]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[4]' during repacking (constrained net name is )
Pb route for Net A[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[4] -> clb[0].I[4]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[3]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[5]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[6]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[3]' on pin 'I[7]' during repacking (constrained net name is )
Pb route for Net A[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[7] -> clb[0].I[7]
Sink nodes:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[2]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[8]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[9]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[10]' during repacking (constrained net name is )
Follow the same mapping results for net 'B[1]' on pin 'I[11]' during repacking (constrained net name is )
Pb route for Net B[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[11] -> clb[0].I[11]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[4]
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[0]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[0]' on pin 'I[12]' during repacking (constrained net name is )
Pb route for Net B[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[12] -> clb[0].I[12]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[1]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[13]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[14]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[15]' during repacking (constrained net name is )
Follow the same mapping results for net 'B[3]' on pin 'I[16]' during repacking (constrained net name is )
Pb route for Net B[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[16] -> clb[0].I[16]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[1]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[1]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n27' on pin 'I[17]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n27:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[17] -> clb[0].I[17]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[3]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[3]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[18]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[19]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[20]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[2]' on pin 'I[21]' during repacking (constrained net name is )
Pb route for Net A[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[21] -> clb[0].I[21]
Sink nodes:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[3]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[3]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[22]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[23]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[24]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[25]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[26]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[27]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[28]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[29]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[30]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[1]' on pin 'I[31]' during repacking (constrained net name is )
Pb route for Net A[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[31] -> clb[0].I[31]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[0]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[32]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[33]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[34]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[35]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[36]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[37]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[38]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[39]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'clk[0]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n35:
Source node:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[0]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[3]
Pb route for Net new_$abc$328$new_n26:
Source node:
	clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[1]
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[0]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[3]
Pb route for Net Y[1]:
Source node:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[11]
Pb route for Net new_$abc$328$new_n30:
Source node:
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[2]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[1]
Pb route for Net new_$abc$328$new_n33:
Source node:
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[12]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[2]
Pb route for Net new_$abc$328$new_n32:
Source node:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[2]
Pb route for Net new_$abc$328$new_n36:
Source node:
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[13]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[5]
Pb route for Net Y[6]:
Source node:
	clb[0]/fle[4]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[4]
Pb route for Net new_$abc$328$new_n31:
Source node:
	clb[0]/fle[5]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[1]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[1]
Pb route for Net new_$abc$328$new_n24:
Source node:
	clb[0]/fle[6]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[6]
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[2]
Pb route for Net new_$abc$328$new_n23:
Source node:
	clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[7]
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[1]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[1]
Pb route for Net Y[5]:
Source node:
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[17]
Pb route for Net new_$abc$328$new_n29:
Source node:
	clb[0]/fle[8]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[0]
Pb route for Net new_$abc$328$new_n22:
Source node:
	clb[0]/fle[9]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[9]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[5]
Added 24 nets to be routed.
Reroute succeed
Update physical pb 'clb[0][default]/fle[0][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n35'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[0][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[1][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n26'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[1][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[1][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[1]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[1][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[2][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n30'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[2][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[2][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n33'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[2][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[3][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n32'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[3][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[3][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n36'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[3][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[4][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[6]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[4][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[5][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n31'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[5][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[6][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n24'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[6][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[7][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n23'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[7][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[7][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[5]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[7][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[8][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n29'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[8][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[4]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[9][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n22'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[9][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Save net 'B[2]' to physical pb_graph_pin 'clb[0].I[0]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0].I[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8].in[4]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0].I[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9].in[5]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[5]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0].I[7]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0].I[11]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[3]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[3]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0].I[12]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0].I[16]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0].I[17]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8].in[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0].I[21]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[4]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[4]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0].I[31]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0].out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0].O[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4].in[3]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1].out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0].O[1]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1].out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0].O[11]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2].out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0].O[2]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7].in[1]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2].out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0].O[12]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3].out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3].out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0].O[13]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4].in[5]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4].out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0].O[4]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5].out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2].in[1]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6].out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0].O[6]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7].out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0].O[7]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7].out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0].O[17]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8].out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7].in[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9].out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0].O[9]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8].in[5]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Saved results in physical pb
Done
Repack clustered block 'new_$abc$328$new_n25'...
Follow the same mapping results for net 'new_$abc$328$new_n30' on pin 'I[0]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n30:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[0] -> clb[0].I[0]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[1]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[2]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[3]' during repacking (constrained net name is )
Follow the same mapping results for net 'new_$abc$328$new_n24' on pin 'I[4]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n24:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[4] -> clb[0].I[4]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n26' on pin 'I[5]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n26:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[5] -> clb[0].I[5]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[3]' on pin 'I[6]' during repacking (constrained net name is )
Pb route for Net B[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[6] -> clb[0].I[6]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[7]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[8]' during repacking (constrained net name is )
Pb route for Net A[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[8] -> clb[0].I[8]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[9]' during repacking (constrained net name is )
Follow the same mapping results for net 'B[0]' on pin 'I[10]' during repacking (constrained net name is )
Pb route for Net B[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[10] -> clb[0].I[10]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n23' on pin 'I[11]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n23:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[11] -> clb[0].I[11]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[1]' on pin 'I[12]' during repacking (constrained net name is )
Pb route for Net A[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[12] -> clb[0].I[12]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n22' on pin 'I[13]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n22:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[13] -> clb[0].I[13]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[2]' on pin 'I[14]' during repacking (constrained net name is )
Pb route for Net A[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[14] -> clb[0].I[14]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[15]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[16]' during repacking (constrained net name is )
Follow the same mapping results for net 'new_$abc$328$new_n36' on pin 'I[17]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n36:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[17] -> clb[0].I[17]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[1]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[1]' on pin 'I[18]' during repacking (constrained net name is )
Pb route for Net B[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[18] -> clb[0].I[18]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[19]' during repacking (constrained net name is )
Follow the same mapping results for net 'new_$abc$328$new_n35' on pin 'I[20]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n35:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[20] -> clb[0].I[20]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[21]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[22]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[23]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[24]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[25]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[26]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[27]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[28]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[29]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[3]' on pin 'I[30]' during repacking (constrained net name is )
Pb route for Net A[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[30] -> clb[0].I[30]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[31]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[32]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[33]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[34]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[35]' during repacking (constrained net name is )
Follow the same mapping results for net 'new_$abc$328$new_n33' on pin 'I[36]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n33:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[36] -> clb[0].I[36]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[37]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[38]' during repacking (constrained net name is )
Follow the same mapping results for net 'B[2]' on pin 'I[39]' during repacking (constrained net name is )
Pb route for Net B[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[39] -> clb[0].I[39]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[1]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'clk[0]' during repacking (constrained net name is )
Pb route for Net Y[0]:
Source node:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[0]
Pb route for Net Y[7]:
Source node:
	clb[0]/fle[4]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[4]
Pb route for Net Y[2]:
Source node:
	clb[0]/fle[5]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[5]
Pb route for Net new_$abc$328$new_n27:
Source node:
	clb[0]/fle[6]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[6]
	clb[0]/fle[7]/ble6[0]/lut6[0].in[1]
Pb route for Net Y[4]:
Source node:
	clb[0]/fle[7]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[7]
Pb route for Net Y[3]:
Source node:
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[18]
Pb route for Net new_$abc$328$new_n25:
Source node:
	clb[0]/fle[9]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[9]
	clb[0]/fle[7]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[1]
Added 23 nets to be routed.
Reroute succeed
Update physical pb 'clb[0][default]/fle[0][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[0]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[0][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[4][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[7]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[4][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[5][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[2]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[5][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[6][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n27'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[6][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[7][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[4]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[7][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[8][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[3]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[8][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[9][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n25'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[9][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0].I[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4].in[5]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0].I[4]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8].in[4]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0].I[5]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7].in[2]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0].I[6]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0].I[8]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0].I[10]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0].I[11]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8].in[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0].I[12]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[4]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[4]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0].I[13]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0].I[14]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0].I[17]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4].in[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0].I[18]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0].I[20]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4].in[2]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0].I[30]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0].I[36]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4].in[0]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0].I[39]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0].out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0].O[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4].out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0].O[4]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5].out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0].O[5]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6].out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0].O[6]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7].in[1]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7].out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0].O[7]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8].out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0].O[18]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9].out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0].O[9]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8].in[1]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[5]'...
Follow the same mapping results for net 'Y[5]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[5]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[5]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[5]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[5]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[5]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[6]'...
Follow the same mapping results for net 'Y[6]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[6]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[6]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[6]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[6]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[6]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[7]'...
Follow the same mapping results for net 'Y[7]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[7]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[7]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[7]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[7]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[7]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[4]'...
Follow the same mapping results for net 'Y[4]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[4]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[4]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[4]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[4]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[4]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[3]'...
Follow the same mapping results for net 'Y[3]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[3]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[3]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[3]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[3]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[3]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[2]'...
Follow the same mapping results for net 'Y[2]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[2]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[2]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[2]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[2]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[2]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[0]'...
Follow the same mapping results for net 'Y[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[0]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[0]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[0]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[0]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[0]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[1]'...
Follow the same mapping results for net 'Y[1]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[1]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[1]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[1]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[1]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[1]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[0]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[0]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[0]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[0]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[0]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[0]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[1]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[1]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[1]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[1]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[1]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[1]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[2]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[2]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[2]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[2]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[2]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[2]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[3]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[3]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[3]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[3]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[3]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[3]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[0]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[0]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[0]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[0]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[0]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[0]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[1]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[1]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[1]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[1]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[1]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[1]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[2]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[2]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[2]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[2]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[2]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[2]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[3]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[3]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[3]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[3]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[3]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[3]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Identify wire LUTs created by repacking
Identified 0 wire LUTs created by repacker
Identify wire LUTs created by repacking took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Build truth tables for physical LUTs
Build truth tables for physical LUTs under clustered block 'new_$abc$328$new_n22'...
Driver atom block: '33'
Pb atom blocks:'33', 
Input nets: new_$abc$328$new_n26  new_$abc$328$new_n23  new_$abc$328$new_n24  new_$abc$328$new_n25  new_$abc$328$new_n27  unconn  
Output net: new_$abc$328$new_n35
Truth table before adaption to fracturable LUT'
	-0-0-- 0
	-01--- 0
	--10-- 0
	0---0- 0
	1---1- 0
Add following truth table to pb_graph_pin 'lut5_out[0]'
	-0-0-1 0
	-01--1 0
	--10-1 0
	0---01 0
	1---11 0

Driver atom block: '24'
Pb atom blocks:'24', '17', 
Input nets: A[1]  B[0]  B[3]  A[0]  B[1]  unconn  
Output net: new_$abc$328$new_n26
Truth table before adaption to fracturable LUT'
	1-1--- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	1-1--1 1

Driver atom block: '17'
Pb atom blocks:'24', '17', 
Input nets: A[1]  B[0]  B[3]  A[0]  B[1]  unconn  
Output net: Y[1]
Truth table before adaption to fracturable LUT'
	0--11- 1
	-0-11- 1
	11-0-- 1
	11--0- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	0--110 1
	-0-110 1
	11-0-0 1
	11--00 1

Driver atom block: '28'
Pb atom blocks:'28', '31', 
Input nets: new_$abc$328$new_n26  new_$abc$328$new_n31  new_$abc$328$new_n32  new_$abc$328$new_n27  unconn  unconn  
Output net: new_$abc$328$new_n30
Truth table before adaption to fracturable LUT'
	-11--- 1
	1-11-- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	-11--1 1
	1-11-1 1

Driver atom block: '31'
Pb atom blocks:'28', '31', 
Input nets: new_$abc$328$new_n26  new_$abc$328$new_n31  new_$abc$328$new_n32  new_$abc$328$new_n27  unconn  unconn  
Output net: new_$abc$328$new_n33
Truth table before adaption to fracturable LUT'
	000--- 1
	-000-- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	000--0 1
	-000-0 1

Driver atom block: '30'
Pb atom blocks:'30', '34', 
Input nets: B[1]  B[3]  A[3]  A[2]  B[2]  unconn  
Output net: new_$abc$328$new_n32
Truth table before adaption to fracturable LUT'
	-101-- 1
	-1-10- 1
	--101- 1
	001-1- 1
	11-1-- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	-101-1 1
	-1-101 1
	--1011 1
	001-11 1
	11-1-1 1

Driver atom block: '34'
Pb atom blocks:'30', '34', 
Input nets: B[1]  B[3]  A[3]  A[2]  B[2]  unconn  
Output net: new_$abc$328$new_n36
Truth table before adaption to fracturable LUT'
	1-111- 0
	-1111- 0
Add following truth table to pb_graph_pin 'lut5_out[1]'
	1-1110 0
	-11110 0

Driver atom block: '32'
Pb atom blocks:'32', 
Input nets: new_$abc$328$new_n30  B[3]  new_$abc$328$new_n33  new_$abc$328$new_n35  A[3]  new_$abc$328$new_n36  
Output net: Y[6]
Truth table before adaption to fracturable LUT'
	1---01 1
	10---1 1
	11--10 1
	0--000 1
	00-0-0 1
	01-011 1
	--0101 1
	-001-1 1
	-10110 1
	0-1-00 1
	001--0 1
	011-11 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	1---01 1
	10---1 1
	11--10 1
	0--000 1
	00-0-0 1
	01-011 1
	--0101 1
	-001-1 1
	-10110 1
	0-1-00 1
	001--0 1
	011-11 1

Driver atom block: '29'
Pb atom blocks:'29', 
Input nets: A[1]  B[0]  B[2]  A[2]  B[1]  A[3]  
Output net: new_$abc$328$new_n31
Truth table before adaption to fracturable LUT'
	1-1110 1
	-10111 1
	111011 1
	111101 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	1-1110 1
	-10111 1
	111011 1
	111101 1

Driver atom block: '22'
Pb atom blocks:'22', 
Input nets: B[1]  A[1]  B[0]  B[2]  A[0]  A[2]  
Output net: new_$abc$328$new_n24
Truth table before adaption to fracturable LUT'
	11-11- 0
	--1111 0
	111--1 0
Add following truth table to pb_graph_pin 'lut6_out[0]'
	11-11- 0
	--1111 0
	111--1 0

Driver atom block: '21'
Pb atom blocks:'21', '26', 
Input nets: new_$abc$328$new_n29  new_$abc$328$new_n30  new_$abc$328$new_n33  B[3]  A[0]  unconn  
Output net: new_$abc$328$new_n23
Truth table before adaption to fracturable LUT'
	---11- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	---111 1

Driver atom block: '26'
Pb atom blocks:'21', '26', 
Input nets: new_$abc$328$new_n29  new_$abc$328$new_n30  new_$abc$328$new_n33  B[3]  A[0]  unconn  
Output net: Y[5]
Truth table before adaption to fracturable LUT'
	01---- 1
	100--- 1
	0-1--- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	01---0 1
	100--0 1
	0-1--0 1

Driver atom block: '27'
Pb atom blocks:'27', 
Input nets: new_$abc$328$new_n27  new_$abc$328$new_n23  new_$abc$328$new_n24  new_$abc$328$new_n26  new_$abc$328$new_n25  new_$abc$328$new_n22  
Output net: new_$abc$328$new_n29
Truth table before adaption to fracturable LUT'
	0-10-- 1
	1-11-- 1
	0--0-0 1
	1--1-0 1
	00-0-- 1
	10-1-- 1
	-01--0 1
	0--00- 1
	1--10- 1
	--1-00 1
	-01-0- 1
	-0--00 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	0-10-- 1
	1-11-- 1
	0--0-0 1
	1--1-0 1
	00-0-- 1
	10-1-- 1
	-01--0 1
	0--00- 1
	1--10- 1
	--1-00 1
	-01-0- 1
	-0--00 1

Driver atom block: '20'
Pb atom blocks:'20', 
Input nets: A[1]  B[2]  B[0]  B[1]  A[2]  A[0]  
Output net: new_$abc$328$new_n22
Truth table before adaption to fracturable LUT'
	101101 1
	111111 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	101101 1
	111111 1

Build truth tables for physical LUTs under clustered block 'new_$abc$328$new_n25'...
Driver atom block: '16'
Pb atom blocks:'16', 
Input nets: A[0]  unconn  unconn  unconn  B[0]  unconn  
Output net: Y[0]
Truth table before adaption to fracturable LUT'
	1---1- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	1---11 1

Driver atom block: '36'
Pb atom blocks:'36', 
Input nets: new_$abc$328$new_n33  new_$abc$328$new_n36  new_$abc$328$new_n35  B[3]  A[3]  new_$abc$328$new_n30  
Output net: Y[7]
Truth table before adaption to fracturable LUT'
	-0-11- 1
	0-111- 1
	001--- 1
	---111 1
	-0---1 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	-0-11- 1
	0-111- 1
	001--- 1
	---111 1
	-0---1 1

Driver atom block: '18'
Pb atom blocks:'18', 
Input nets: A[0]  B[0]  A[1]  A[2]  B[1]  B[2]  
Output net: Y[2]
Truth table before adaption to fracturable LUT'
	00--0- 0
	000--- 0
	-0--00 0
	-00--0 0
	101-11 0
	0--00- 0
	0-00-- 0
	11-0-0 0
	01111- 0
	11-1-1 0
Add following truth table to pb_graph_pin 'lut6_out[0]'
	00--0- 0
	000--- 0
	-0--00 0
	-00--0 0
	101-11 0
	0--00- 0
	0-00-- 0
	11-0-0 0
	01111- 0
	11-1-1 0

Driver atom block: '25'
Pb atom blocks:'25', 
Input nets: A[1]  A[2]  B[1]  B[0]  B[2]  A[3]  
Output net: new_$abc$328$new_n27
Truth table before adaption to fracturable LUT'
	--0-0- 0
	-0---0 0
	----00 0
	000--- 0
	1-1--0 0
	-000-- 0
	011011 0
	-1-10- 0
	10111- 0
	1101-1 0
Add following truth table to pb_graph_pin 'lut6_out[0]'
	--0-0- 0
	-0---0 0
	----00 0
	000--- 0
	1-1--0 0
	-000-- 0
	011011 0
	-1-10- 0
	10111- 0
	1101-1 0

Driver atom block: '19'
Pb atom blocks:'19', 
Input nets: new_$abc$328$new_n25  new_$abc$328$new_n27  new_$abc$328$new_n26  new_$abc$328$new_n22  new_$abc$328$new_n23  new_$abc$328$new_n24  
Output net: Y[4]
Truth table before adaption to fracturable LUT'
	00100- 1
	01000- 1
	00011- 1
	01111- 1
	10010- 1
	11110- 1
	10001- 1
	11101- 1
	-00100 1
	-11100 1
	-00010 1
	-11010 1
	1000-0 1
	1110-0 1
	101110 1
	110110 1
	-01001 1
	-10001 1
	-00111 1
	-11111 1
	0010-1 1
	0100-1 1
	001-01 1
	010-01 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	00100- 1
	01000- 1
	00011- 1
	01111- 1
	10010- 1
	11110- 1
	10001- 1
	11101- 1
	-00100 1
	-11100 1
	-00010 1
	-11010 1
	1000-0 1
	1110-0 1
	101110 1
	110110 1
	-01001 1
	-10001 1
	-00111 1
	-11111 1
	0010-1 1
	0100-1 1
	001-01 1
	010-01 1

Driver atom block: '35'
Pb atom blocks:'35', 
Input nets: new_$abc$328$new_n23  new_$abc$328$new_n25  unconn  new_$abc$328$new_n22  new_$abc$328$new_n24  unconn  
Output net: Y[3]
Truth table before adaption to fracturable LUT'
	00-00- 1
	10-10- 1
	00-11- 1
	10-01- 1
	01-10- 1
	11-00- 1
	01-01- 1
	11-11- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	00-000 1
	10-100 1
	00-110 1
	10-010 1
	01-100 1
	11-000 1
	01-010 1
	11-110 1

Driver atom block: '23'
Pb atom blocks:'23', 
Input nets: B[1]  B[2]  B[0]  A[2]  A[1]  A[3]  
Output net: new_$abc$328$new_n25
Truth table before adaption to fracturable LUT'
	01--10 1
	-1-010 1
	1--100 1
	10-1-0 1
	010-1- 1
	-1001- 1
	1-010- 1
	1001-- 1
	0-1-01 1
	001--1 1
	--1001 1
	-010-1 1
	111111 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	01--10 1
	-1-010 1
	1--100 1
	10-1-0 1
	010-1- 1
	-1001- 1
	1-010- 1
	1001-- 1
	0-1-01 1
	001--1 1
	--1001 1
	-010-1 1
	111111 1

Build truth tables for physical LUTs under clustered block 'out:Y[5]'...
Build truth tables for physical LUTs under clustered block 'out:Y[6]'...
Build truth tables for physical LUTs under clustered block 'out:Y[7]'...
Build truth tables for physical LUTs under clustered block 'out:Y[4]'...
Build truth tables for physical LUTs under clustered block 'out:Y[3]'...
Build truth tables for physical LUTs under clustered block 'out:Y[2]'...
Build truth tables for physical LUTs under clustered block 'out:Y[0]'...
Build truth tables for physical LUTs under clustered block 'out:Y[1]'...
Build truth tables for physical LUTs under clustered block 'A[0]'...
Build truth tables for physical LUTs under clustered block 'A[1]'...
Build truth tables for physical LUTs under clustered block 'A[2]'...
Build truth tables for physical LUTs under clustered block 'A[3]'...
Build truth tables for physical LUTs under clustered block 'B[0]'...
Build truth tables for physical LUTs under clustered block 'B[1]'...
Build truth tables for physical LUTs under clustered block 'B[2]'...
Build truth tables for physical LUTs under clustered block 'B[3]'...
Build truth tables for physical LUTs took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml

Confirm selected options when call command 'build_architecture_bitstream':
--write_file: fabric_indepenent_bitstream.xml
--read_file: off
--no_time_stamp: off
--verbose: off

Build fabric-independent bitstream for implementation 'mult4'

Generating bitstream for Switch blocks...Done
Generating bitstream for X-direction Connection blocks ...Done
Generating bitstream for Y-direction Connection blocks ...Done

Build fabric-independent bitstream for implementation 'mult4'
 took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Overwrite Bitstream


Overwrite Bitstream
 took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Warning 35: Directory path is empty and nothing will be created.
Write 8416 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
Write 8416 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.01 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Build non-fabric bitstream for implementation 'mult4'


Build non-fabric bitstream for implementation 'mult4'
 took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: build_fabric_bitstream

Confirm selected options when call command 'build_fabric_bitstream':
--verbose: off

Build fabric dependent bitstream


Build fabric dependent bitstream
 took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit --no_time_stamp

Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.bit
--format: plain_text
--filter_value: off
--path_only: off
--value_only: off
--trim_path: off
--fast_configuration: off
--keep_dont_care_bits: off
--wl_decremental_order: off
--no_time_stamp: on
--verbose: off
Warning 36: Directory path is empty and nothing will be created.
Write 8416 fabric bitstream into plain text file 'fabric_bitstream.bit'
Write 8416 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml --no_time_stamp

Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.xml
--format: xml
--filter_value: off
--path_only: off
--value_only: off
--trim_path: off
--fast_configuration: off
--keep_dont_care_bits: off
--wl_decremental_order: off
--no_time_stamp: on
--verbose: off
Warning 37: Directory path is empty and nothing will be created.
Write 8416 fabric bitstream into xml file 'fabric_bitstream.xml'
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Write 8416 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_hierarchy --file ./fabric_hierarchy.txt

Confirm selected options when call command 'write_fabric_hierarchy':
--file, -f: ./fabric_hierarchy.txt
--module: off
--filter: off
--depth: off
--exclude_empty_modules: off
--verbose: off
Write fabric hierarchy to plain-text file './fabric_hierarchy.txt'
Outputted 1 modules as root
Write fabric hierarchy to plain-text file './fabric_hierarchy.txt' took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_io_info --file ./fabric_io_location.xml --verbose

Confirm selected options when call command 'write_fabric_io_info':
--file, -f: ./fabric_io_location.xml
--no_time_stamp: off
--verbose: on
Warning 38: Directory '.' already exists. Will overwrite contents
Write fabric I/O information to an XML file './fabric_io_location.xml'
Outputted 64 I/Os to XML file: ./fabric_io_location.xml
Write fabric I/O information to an XML file './fabric_io_location.xml' took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_verilog --file /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose

Confirm selected options when call command 'write_fabric_verilog':
--file, -f: /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC
--constant_undriven_inputs: off
--explicit_port_mapping: on
--include_timing: on
--print_user_defined_template: on
--default_net_type: off
--no_time_stamp: off
--use_relative_path: off
--little_endian, -le: off
--verbose: on
Write Verilog netlists for FPGA fabric

Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC'
Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module'
Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb'
Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/routing'
Generating Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/inv_buf_passgate.v' for essential gates...Done
Writing Verilog netlist for configuration decoders '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/arch_encoder.v'...Done
Writing Verilog netlist for local decoders for multiplexers '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/local_encoder.v'...Done
Writing Verilog netlist for Multiplexer primitives '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/mux_primitives.v' ...Done
Writing Verilog netlist for Multiplexers '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/muxes.v' ...Done
Writing Verilog netlist for LUTs '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.v'...Done
Writing Verilog netlist for wires '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/wires.v'...Done
Writing Verilog netlist for memories '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/memories.v' ...Done
Writing Verilog netlist for shift register banks '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/shift_register_banks.v' ...Done
Creating template for user-defined Verilog modules '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_templates.v'...Done

Writing logical tiles...
Writing Verilog netlists for logic tile 'io' ...
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_io_mode_physical__iopad.v' for primitive pb_type 'iopad' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_io_mode_physical__iopad'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_io_mode_io_.v' for pb_type 'io' ...
Writing Verilog codes of pb_type 'logical_tile_io_mode_io_'...Done
Done

Writing Verilog netlists for logic tile 'clb' ...
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut6.v' for primitive pb_type 'frac_lut6' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut6'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v' for pb_type 'frac_logic' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v' for primitive pb_type 'ff' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v' for pb_type 'fabric' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle.v' for pb_type 'fle' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_clb_.v' for pb_type 'clb' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_clb_'...Done
Done

Writing logical tiles...Done

Building physical tiles...
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_top.v' for physical tile 'io' at top side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_right.v' for physical tile 'io' at right side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_bottom.v' for physical tile 'io' at bottom side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_left.v' for physical tile 'io' at left side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_clb.v' for physical_tile 'clb'...Done
Building physical tiles...Done

Writing Verilog netlist for top-level module of FPGA fabric '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/fpga_top.v'...Done
Written 74 Verilog modules in total
Write Verilog netlists for FPGA fabric
 took 0.02 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: write_full_testbench --file ./SRC --reference_benchmark_file_path mult4_output_verilog.v --explicit_port_mapping --bitstream fabric_bitstream.bit --simulator iverilog

Confirm selected options when call command 'write_full_testbench':
--file, -f: ./SRC
--dut_module: off
--bitstream: fabric_bitstream.bit
--simulator: iverilog
--fabric_netlist_file_path: off
--pin_constraints_file, -pcf: off
--bus_group_file, -bgf: off
--reference_benchmark_file_path: mult4_output_verilog.v
--fast_configuration: off
--explicit_port_mapping: on
--default_net_type: off
--no_self_checking: off
--include_signal_init: off
--no_time_stamp: off
--use_relative_path: off
--little_endian, -le: off
--verbose: off
Write Verilog full testbenches for FPGA fabric

# Write autocheck testbench for FPGA top-level Verilog netlist for 'mult4'
Will use 8417 configuration clock cycles to top testbench
# Write autocheck testbench for FPGA top-level Verilog netlist for 'mult4' took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Write Verilog full testbenches for FPGA fabric
 took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: write_pnr_sdc --file ./SDC

Confirm selected options when call command 'write_pnr_sdc':
--file, -f: ./SDC
--flatten_names: off
--hierarchical: off
--output_hierarchy: off
--time_unit: off
--constrain_global_port: off
--constrain_non_clock_global_port: off
--constrain_grid: off
--constrain_sb: off
--constrain_cb: off
--constrain_configurable_memory_outputs: off
--constrain_routing_multiplexer_outputs: off
--constrain_switch_block_outputs: off
--constrain_zero_delay_paths: off
--no_time_stamp: off
--verbose: off
Succeed to create directory './SDC'
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc'
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc'
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc'
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.01 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc'
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Write SDC for constrain Switch Block timing for P&R flow
Write SDC for constrain Switch Block timing for P&R flow took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Write SDC for constrain Connection Block timing for P&R flow
Write SDC for constrain Connection Block timing for P&R flow took 0.00 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)
Write SDC for constraining grid timing for P&R flow
Write SDC for constraining grid timing for P&R flow took 0.01 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc

Confirm selected options when call command 'write_sdc_disable_timing_configure_ports':
--file, -f: ./SDC/disable_configure_ports.sdc
--flatten_names: off
--no_time_stamp: off
--verbose: off
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc'
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.01 seconds (max_rss 64.4 MiB, delta_rss +0.0 MiB)

Command line to execute: exit

Confirm selected options when call command 'exit':

Finish execution with 0 errors

The entire OpenFPGA flow took 0.156718 seconds

Thank you for using OpenFPGA!
Incr Slack updates 35 in 3.6227e-05 sec
Full Max Req/Worst Slack updates 7 in 4.723e-06 sec
Incr Max Req/Worst Slack updates 28 in 1.2597e-05 sec
Incr Criticality updates 19 in 3.6465e-05 sec
Full Criticality updates 16 in 2.8394e-05 sec
0

[shimoshida]

Since it’s a bit long, I’ll summarize the reproduction steps here again.

Modified ones

task.conf

[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
# fpga_flow=yosys_vpr
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml 

[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga

openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
# Use a absolute path for the Verilog netlists to be generated
# This is designed to allow the test case 'basic_tests/generate_testbench'
# to use the Verilog netlists along with testbenches in HDL simulation
openfpga_verilog_output_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=20

[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml

[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult4/mult4.blif

[SYNTHESIS_PARAM]
bench0_top = mult4
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult4/mult4.v
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult4/mult4.act

[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

mult4.blif

# Benchmark "mult4" written by ABC on Sat Jan 24 18:54:44 2026
.model mult4
.inputs A[0] A[1] A[2] A[3] B[0] B[1] B[2] B[3] 
.outputs Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] 
.names B[0] A[0] Y[0]
11 1
.names B[0] A[1] B[1] A[0] Y[1]
-011 1
0-11 1
11-0 1
110- 1
.names A[2] B[2] A[1] B[1] B[0] A[0] Y[2]
---000 0
--0-00 0
-0-00- 0
-00-0- 0
-11101 0
0--0-0 0
0-0--0 0
00--11 0
1-1110 0
11--11 0
.names new_$abc$328$new_n24 new_$abc$328$new_n25 new_$abc$328$new_n23 \
 new_$abc$328$new_n22 new_$abc$328$new_n27 new_$abc$328$new_n26 Y[4]
-00001 1
-00010 1
-01100 1
-01111 1
-10100 1
-10111 1
-11000 1
-11011 1
0-0100 1
0-0111 1
0-1000 1
0-1011 1
01-000 1
01-011 1
011101 1
011110 1
1-0001 1
1-0010 1
1-1100 1
1-1111 1
10-001 1
10-010 1
100-01 1
100-10 1
.names B[2] A[2] A[0] A[1] B[1] B[0] new_$abc$328$new_n22
001111 1
111111 1
.names B[3] A[0] new_$abc$328$new_n23
11 1
.names A[2] B[0] B[1] A[1] B[2] A[0] new_$abc$328$new_n24
--1111 0
11--11 0
1111-- 0
.names B[0] A[2] B[1] A[3] B[2] A[1] new_$abc$328$new_n25
--0011 1
-0-011 1
-110-0 1
-1100- 1
0-0-11 1
00--11 1
011--0 1
011-0- 1
1-01-0 1
1-010- 1
10-1-0 1
10-10- 1
111111 1
.names B[3] A[1] new_$abc$328$new_n26
11 1
.names B[0] A[1] A[3] B[2] A[2] B[1] new_$abc$328$new_n27
---0-0 0
--0-0- 0
--00-- 0
-0--00 0
-10--1 0
0---00 0
001111 0
1--01- 0
11-101 0
111-10 0
.names new_$abc$328$new_n33 new_$abc$328$new_n30 new_$abc$328$new_n29 Y[5]
-10 1
001 1
1-0 1
.names new_$abc$328$new_n25 new_$abc$328$new_n23 new_$abc$328$new_n22 \
 new_$abc$328$new_n24 new_$abc$328$new_n26 new_$abc$328$new_n27 \
 new_$abc$328$new_n29
---100 1
---111 1
--0-00 1
--0-11 1
-0--00 1
-0--11 1
-001-- 1
0---00 1
0---11 1
0-01-- 1
00-1-- 1
000--- 1
.names new_$abc$328$new_n27 new_$abc$328$new_n26 new_$abc$328$new_n31 \
 new_$abc$328$new_n32 new_$abc$328$new_n30
--11 1
11-1 1
.names B[0] A[1] A[2] B[1] A[3] B[2] new_$abc$328$new_n31
-11101 1
1-1110 1
110111 1
111011 1
.names B[1] B[2] A[3] A[2] B[3] new_$abc$328$new_n32
--011 1
-0-11 1
-110- 1
011-0 1
1--11 1
.names new_$abc$328$new_n27 new_$abc$328$new_n26 new_$abc$328$new_n32 \
 new_$abc$328$new_n31 new_$abc$328$new_n33
-000 1
0-00 1
.names new_$abc$328$new_n33 new_$abc$328$new_n35 B[3] A[3] \
 new_$abc$328$new_n30 new_$abc$328$new_n36 Y[6]
---011 1
--0-11 1
--1110 1
-0-000 1
-00-00 1
-01101 1
01-0-1 1
010--1 1
0111-0 1
1--000 1
1-0-00 1
1-1101 1
.names new_$abc$328$new_n27 new_$abc$328$new_n26 new_$abc$328$new_n24 \
 new_$abc$328$new_n25 new_$abc$328$new_n23 new_$abc$328$new_n35
---00 0
--1-0 0
--10- 0
00--- 0
11--- 0
.names B[3] B[1] A[3] A[2] B[2] new_$abc$328$new_n36
-1111 0
1-111 0
.names new_$abc$328$new_n25 new_$abc$328$new_n24 new_$abc$328$new_n23 \
 new_$abc$328$new_n22 Y[3]
0000 1
0011 1
0101 1
0110 1
1001 1
1010 1
1100 1
1111 1
.names new_$abc$328$new_n30 new_$abc$328$new_n33 new_$abc$328$new_n35 \
 new_$abc$328$new_n36 A[3] B[3] Y[7]
---011 1
-01-11 1
-010-- 1
1---11 1
1--0-- 1
.end

generate_fabric_example_script.openfpga

# Run VPR for the 'and' design
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH}

# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}

# Annotate the OpenFPGA architecture to VPR data base
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges

# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

# Build the module graph
build_fabric --compress_routing #--verbose


# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack --verbose


build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml

build_fabric_bitstream
write_fabric_bitstream --format plain_text --file fabric_bitstream.bit --no_time_stamp
write_fabric_bitstream --format xml --file fabric_bitstream.xml --no_time_stamp


# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt

# Write the fabric I/O attributes to a file
# This is used by pin constraint files
write_fabric_io_info --file ./fabric_io_location.xml --verbose

# Write the Verilog netlist for FPGA fabric
write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose

write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --bitstream fabric_bitstream.bit --simulator iverilog

# Write the SDC files for PnR backend
#  - Turn on every options here
write_pnr_sdc --file ./SDC

# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc

# Finish and exit OpenFPGA
exit

Reproduction Procedure

1. Set path via source openfpga.sh
2. Put the above files to corresponding directory

• mult4.blif: ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult4/mult4.blif
• task.conf: ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf
• generate_fabric_example_script.openfpga: ${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga

3. Run python openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric, and std log is shown as

  moshida-B760-Pro-RS-D4  moshida   master  ~  OpenFPGA  1  python openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric
/home/moshida/.pyenv/versions/3.12.3/lib/python3.12/site-packages/humanize/__init__.py:2: UserWarning: pkg_resources is deprecated as an API. See https://setuptools.pypa.io/en/latest/pkg_resources.html. The pkg_resources package is slated for removal as early as 2025-11-30. Refrain from using this package or pin to Setuptools<81.
  import pkg_resources
 INFO (     MainThread) - Set up to run 2 Parallel threads
 INFO (     MainThread) - Currently running task basic_tests/generate_fabric
 INFO (     MainThread) - Created "run027" directory for current task run
 INFO (     MainThread) - Running "vpr_blif" flow
 INFO (     MainThread) - Found 1 Architectures 1 Benchmarks & 1 Script Parameters
 INFO (     MainThread) - Created total 1 jobs
 INFO (00_mult4_MIN_ROUTE_CHAN_WIDTH) - 00_mult4_MIN_ROUTE_CHAN_WIDTH Finished with returncode 0, Time Taken a moment
 INFO (00_mult4_MIN_ROUTE_CHAN_WIDTH) - ***** 0 runs pending *****
 INFO (     MainThread) - Task execution completed

4. Move to the generated ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH directory, and save the shell script for simulation

run_xsim.sh

#!/bin/bash

if [ -d "xsim.dir" ]; then
    rm -rf "xsim.dir"
    echo "Deleted xsim.dir"
fi

xvlog ./SRC/mult4_include_netlists.v ./SRC/mult4_autocheck_top_tb.v
xelab mult4_autocheck_top_tb
xsim mult4_autocheck_top_tb -runall

5. Fix generated verilog files in SRC directory. nettype none is replaced with wire.
6. Fix generated testbench file from

	mult4 REF_DUT(
		.A_0_(A_0__shared_input),
		.A_1_(A_1__shared_input),
		.A_2_(A_2__shared_input),
		.A_3_(A_3__shared_input),
		.B_0_(B_0__shared_input),
		.B_1_(B_1__shared_input),
		.B_2_(B_2__shared_input),
		.B_3_(B_3__shared_input),
		.Y_0_(Y_0__benchmark),
		.Y_1_(Y_1__benchmark),
		.Y_2_(Y_2__benchmark),
		.Y_3_(Y_3__benchmark),
		.Y_4_(Y_4__benchmark),
		.Y_5_(Y_5__benchmark),
		.Y_6_(Y_6__benchmark),
		.Y_7_(Y_7__benchmark)
	);

to

	mult4 REF_DUT(
		.A({A_3__shared_input,
		    A_2__shared_input,
		    A_1__shared_input,
		    A_0__shared_input}),
		.B({B_3__shared_input,
		    B_2__shared_input,
		    B_1__shared_input,
		    B_0__shared_input}),
		.Y({Y_7__benchmark,
		    Y_6__benchmark,
		    Y_5__benchmark,
		    Y_4__benchmark,
		    Y_3__benchmark,
		    Y_2__benchmark,
		    Y_1__benchmark,
		    Y_0__benchmark})
	);

to be compatible with the yosys-generated file(mult4_output_verilog.v).

module mult4 (A, B, Y);
  input  wire [3:0]  A;
  input  wire [3:0]  B;
  output wire [7:0] Y;
  assign Y = A * B;
endmodule

7. Runchmod +x ./run_xsim.sh and ./run_xsim.sh, then get the log

Simulation start
Mismatch on Y_5__fpga at time =           84187.61ns
Mismatch on Y_7__fpga at time =           84187.61ns
Mismatch on Y_3__fpga at time =           84191.13ns
Mismatch on Y_4__fpga at time =           84191.13ns
Mismatch on Y_6__fpga at time =           84191.13ns
Mismatch on Y_7__fpga at time =           84194.65ns
Mismatch on Y_4__fpga at time =           84198.18ns
Mismatch on Y_6__fpga at time =           84198.18ns
Mismatch on Y_3__fpga at time =           84201.70ns
Mismatch on Y_4__fpga at time =           84205.22ns
Mismatch on Y_6__fpga at time =           84205.22ns
Mismatch on Y_5__fpga at time =           84208.74ns
Mismatch on Y_5__fpga at time =           84215.79ns
Mismatch on Y_5__fpga at time =           84222.83ns
Mismatch on Y_7__fpga at time =           84222.83ns
Mismatch on Y_3__fpga at time =           84229.87ns
Mismatch on Y_5__fpga at time =           84229.87ns
Mismatch on Y_7__fpga at time =           84229.87ns
Mismatch on Y_3__fpga at time =           84236.92ns
Mismatch on Y_4__fpga at time =           84236.92ns
Mismatch on Y_5__fpga at time =           84236.92ns
Mismatch on Y_6__fpga at time =           84236.92ns
Mismatch on Y_7__fpga at time =           84236.92ns
Simulation Failed with          23 error(s)
$finish called at time : 84240 ns : File "/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run027/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/mult4_autocheck_top_tb.v" Line 496

Waveform Check

The waveform presented in the initial comment is a reformatted view created in the testbench, such as by grouping signals for better readability. The underlying simulation steps and procedure remain unchanged.

1. Fix run_xsim.sh

#!/bin/bash

if [ -d "xsim.dir" ]; then
    rm -rf "xsim.dir"
    echo "Deleted xsim.dir"
fi

xvlog ./SRC/mult4_include_netlists.v ./SRC/mult4_autocheck_top_tb.v
xelab mult4_autocheck_top_tb -debug all
xsim mult4_autocheck_top_tb -wdb mult4_autocheck_top_tb.wdb -tclbatch xsim_log_waveform.tcl
xsim -gui mult4_autocheck_top_tb.wdb

2. Add xsim_log_waveform.tcl

log_wave -r *
run all
quit

3. Run ./run_xsim.sh

[tangxifan]

@shimoshida Thank you for the details. Based on the files that you have shared, there are a few things to try for debugging:

• How is mult4.blif obtained? If you are using Yosys, you can try the yosys_vpr flow in the openfpga task configuration YAML.
• Have you checked the logic equivalence between the mult4.blif and the Verilog file? Yosys can convert the blif to Verilog
• Can you try to add --constant_method_method route to vpr in your openfpga shell script ? See details here
• Can you share the openfpgashell.log under ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH?

If the problem insists after trying all above, I will try to add a testcase on mult4 based on your generate_fabric but will use Yosys-vpr flow.

Suggestions to simplify your flow:

• You may use the option --default_nettype wire when calling command write_full_testbench , write_fabric_verilog etc. See details in doc
• You can use the bus_group_gen.py to avoid manually modify testbench file.

[shimoshida]

@tangxifan Sorry for late response.

• How is mult4.blif obtained? If you are using Yosys, you can try the yosys_vpr flow in the openfpga task configuration YAML.
• Have you checked the logic equivalence between the mult4.blif and the Verilog file? Yosys can convert the blif to Verilog

Originally, I ran the flow using mult4.v as input with yosys_vpr. The generated mult4_output_verilog.v requires manual modification to run simulation, and reporting that in an issue on GitHub would make the discussion more complicated. Therefore, I am reporting the issue using vpr_vlif with the mult4.blif generated by yosys_vpr as input instead. When the input mult4.v is

module mult4 (A, B, Y);
  input  wire [3:0]  A;
  input  wire [3:0]  B;
  output wire [7:0] Y;
  assign Y = A * B;
endmodule

the following is obtained by using yosys_vpr,

mult4_output_verilog.v

/* Generated by Yosys 0.56+30 (git sha1 407d42511, g++ 11.4.0-1ubuntu1~22.04.2 -fPIC -O3) */

module mult4(\A[0] , \A[1] , \A[2] , \A[3] , \B[0] , \B[1] , \B[2] , \B[3] , \Y[0] , \Y[1] , \Y[2] , \Y[3] , \Y[4] , \Y[5] , \Y[6] , \Y[7] );
  input \A[0] ;
  wire \A[0] ;
  input \A[1] ;
  wire \A[1] ;
  input \A[2] ;
  wire \A[2] ;
  input \A[3] ;
  wire \A[3] ;
  input \B[0] ;
  wire \B[0] ;
  input \B[1] ;
  wire \B[1] ;
  input \B[2] ;
  wire \B[2] ;
  input \B[3] ;
  wire \B[3] ;
  output \Y[0] ;
  wire \Y[0] ;
  output \Y[1] ;
  wire \Y[1] ;
  output \Y[2] ;
  wire \Y[2] ;
  output \Y[3] ;
  wire \Y[3] ;
  output \Y[4] ;
  wire \Y[4] ;
  output \Y[5] ;
  wire \Y[5] ;
  output \Y[6] ;
  wire \Y[6] ;
  output \Y[7] ;
  wire \Y[7] ;
  wire \new_$abc$328$new_n22 ;
  wire \new_$abc$328$new_n23 ;
  wire \new_$abc$328$new_n24 ;
  wire \new_$abc$328$new_n25 ;
  wire \new_$abc$328$new_n26 ;
  wire \new_$abc$328$new_n27 ;
  wire \new_$abc$328$new_n29 ;
  wire \new_$abc$328$new_n30 ;
  wire \new_$abc$328$new_n31 ;
  wire \new_$abc$328$new_n32 ;
  wire \new_$abc$328$new_n33 ;
  wire \new_$abc$328$new_n35 ;
  wire \new_$abc$328$new_n36 ;
  assign \Y[0]  = 4'h8 >> { \A[0] , \B[0]  };
  assign \new_$abc$328$new_n27  = 64'he35070f07f008000 >> { \B[1] , \A[2] , \B[2] , \A[3] , \A[1] , \B[0]  };
  assign \Y[5]  = 8'h1e >> { \new_$abc$328$new_n29 , \new_$abc$328$new_n30 , \new_$abc$328$new_n33  };
  assign \new_$abc$328$new_n29  = 64'hff7f17011701ff7f >> { \new_$abc$328$new_n27 , \new_$abc$328$new_n26 , \new_$abc$328$new_n24 , \new_$abc$328$new_n22 , \new_$abc$328$new_n23 , \new_$abc$328$new_n25  };
  assign \new_$abc$328$new_n30  = 16'hf800 >> { \new_$abc$328$new_n32 , \new_$abc$328$new_n31 , \new_$abc$328$new_n26 , \new_$abc$328$new_n27  };
  assign \new_$abc$328$new_n31  = 64'h0880c000a0000000 >> { \B[2] , \A[3] , \B[1] , \A[2] , \A[1] , \B[0]  };
  assign \new_$abc$328$new_n32  = 32'd3217047744 >> { \B[3] , \A[2] , \A[3] , \B[2] , \B[1]  };
  assign \new_$abc$328$new_n33  = 16'h0007 >> { \new_$abc$328$new_n31 , \new_$abc$328$new_n32 , \new_$abc$328$new_n26 , \new_$abc$328$new_n27  };
  assign \Y[6]  = 64'h0fffb444f0004bbb >> { \new_$abc$328$new_n36 , \new_$abc$328$new_n30 , \A[3] , \B[3] , \new_$abc$328$new_n35 , \new_$abc$328$new_n33  };
  assign \new_$abc$328$new_n35  = 32'd1711670784 >> { \new_$abc$328$new_n23 , \new_$abc$328$new_n25 , \new_$abc$328$new_n24 , \new_$abc$328$new_n26 , \new_$abc$328$new_n27  };
  assign \new_$abc$328$new_n36  = 32'd536870911 >> { \B[2] , \A[2] , \A[3] , \B[1] , \B[3]  };
  assign \Y[1]  = 16'h7888 >> { \A[0] , \B[1] , \A[1] , \B[0]  };
  assign \Y[3]  = 16'h9669 >> { \new_$abc$328$new_n22 , \new_$abc$328$new_n23 , \new_$abc$328$new_n24 , \new_$abc$328$new_n25  };
  assign \Y[7]  = 64'hbaff00ba00ba00ba >> { \B[3] , \A[3] , \new_$abc$328$new_n36 , \new_$abc$328$new_n35 , \new_$abc$328$new_n33 , \new_$abc$328$new_n30  };
  assign \Y[2]  = 64'h66663ccc5aaaf000 >> { \A[0] , \B[0] , \B[1] , \A[1] , \B[2] , \A[2]  };
  assign \Y[4]  = 64'hbdd4422b422bbdd4 >> { \new_$abc$328$new_n26 , \new_$abc$328$new_n27 , \new_$abc$328$new_n22 , \new_$abc$328$new_n23 , \new_$abc$328$new_n25 , \new_$abc$328$new_n24  };
  assign \new_$abc$328$new_n22  = 64'h9000000000000000 >> { \B[0] , \B[1] , \A[1] , \A[0] , \A[2] , \B[2]  };
  assign \new_$abc$328$new_n23  = 4'h8 >> { \A[0] , \B[3]  };
  assign \new_$abc$328$new_n24  = 64'h07777fff7fff7fff >> { \A[0] , \B[2] , \A[1] , \B[1] , \B[0] , \A[2]  };
  assign \new_$abc$328$new_n25  = 64'h953f6ac06ac06ac0 >> { \A[1] , \B[2] , \A[3] , \B[1] , \A[2] , \B[0]  };
  assign \new_$abc$328$new_n26  = 4'h8 >> { \A[1] , \B[3]  };
endmodule

and the following is a part of generated testbench

	mult4 REF_DUT(
		.A_0_(A_0__shared_input),
		.A_1_(A_1__shared_input),
		.A_2_(A_2__shared_input),
		.A_3_(A_3__shared_input),
		.B_0_(B_0__shared_input),
		.B_1_(B_1__shared_input),
		.B_2_(B_2__shared_input),
		.B_3_(B_3__shared_input),
		.Y_0_(Y_0__benchmark),
		.Y_1_(Y_1__benchmark),
		.Y_2_(Y_2__benchmark),
		.Y_3_(Y_3__benchmark),
		.Y_4_(Y_4__benchmark),
		.Y_5_(Y_5__benchmark),
		.Y_6_(Y_6__benchmark),
		.Y_7_(Y_7__benchmark)
	);

In this case, errors of port mismatch occur as follows

ERROR: [VRFC 10-3180] cannot find port 'Y_7_' on this module [/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run065/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/mult4_autocheck_top_tb.v:290]
ERROR: [VRFC 10-3180] cannot find port 'Y_6_' on this module [/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run065/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/mult4_autocheck_top_tb.v:289]
ERROR: [VRFC 10-3180] cannot find port 'Y_5_' on this module [/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run065/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/mult4_autocheck_top_tb.v:288]
ERROR: [VRFC 10-3180] cannot find port 'Y_4_' on this module [/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run065/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/mult4_autocheck_top_tb.v:287]

Even when I run the simulation using the input file mult4.v (instead of the generated mult4_output_verilog.v), the same simulation error occurs.

The instance definition part in the modified testbench.

	mult4 REF_DUT(
		.A({A_3__shared_input, A_2__shared_input, A_1__shared_input, A_0__shared_input}),
		.B({B_3__shared_input, B_2__shared_input, B_1__shared_input, B_0__shared_input}),
		.Y({Y_7__benchmark, Y_6__benchmark, Y_5__benchmark, Y_4__benchmark, Y_3__benchmark, Y_2__benchmark, Y_1__benchmark, Y_0__benchmark})
	);

Result...

Simulation start
Mismatch on Y_1__fpga at time =           84187.61ns
Mismatch on Y_2__fpga at time =           84187.61ns
Mismatch on Y_3__fpga at time =           84187.61ns
Mismatch on Y_4__fpga at time =           84187.61ns
Mismatch on Y_5__fpga at time =           84187.61ns
Mismatch on Y_6__fpga at time =           84187.61ns
Mismatch on Y_7__fpga at time =           84187.61ns
Mismatch on Y_2__fpga at time =           84194.65ns
Mismatch on Y_7__fpga at time =           84194.65ns
Mismatch on Y_0__fpga at time =           84198.18ns
Mismatch on Y_1__fpga at time =           84198.18ns
Mismatch on Y_2__fpga at time =           84201.70ns
Mismatch on Y_1__fpga at time =           84208.74ns
Mismatch on Y_2__fpga at time =           84208.74ns
Mismatch on Y_7__fpga at time =           84212.26ns
Mismatch on Y_2__fpga at time =           84215.79ns
Mismatch on Y_0__fpga at time =           84222.83ns
Mismatch on Y_1__fpga at time =           84222.83ns
Mismatch on Y_2__fpga at time =           84222.83ns
Mismatch on Y_7__fpga at time =           84222.83ns
Mismatch on Y_0__fpga at time =           84229.87ns
Mismatch on Y_7__fpga at time =           84229.87ns
Mismatch on Y_2__fpga at time =           84236.92ns

openfpgashell.log when I ran the flow using mult4.v as input with yosys_vpr is here.

openfpgashell.log

/home/moshida/OpenFPGA/build/openfpga/openfpga -batch -f mult4_run.openfpga
Reading script file mult4_run.openfpga...

            ___                   _____ ____   ____    _     
           / _ \ _ __   ___ _ __ |  ___|  _ \ / ___|  / \    
          | | | | '_ \ / _ \ '_ \| |_  | |_) | |  _  / _ \   
          | |_| | |_) |  __/ | | |  _| |  __/| |_| |/ ___ \  
           \___/| .__/ \___|_| |_|_|   |_|    \____/_/   \_\ 
                |_|                                          

               OpenFPGA: An Open-source FPGA IP Generator
                     Versatile Place and Route (VPR)
                           FPGA-Verilog
                           FPGA-SPICE
                           FPGA-SDC
                           FPGA-Bitstream

             This is a free software under the MIT License

             Copyright (c) 2018 LNIS - The University of Utah

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.



Command line to execute: vpr /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run065/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_tileable_40nm.xml mult4.blif --clock_modeling route --device 2x2 --route_chan_width 20 --skip_sync_clustering_and_routing_results on
VPR FPGA Placement and Routing.
Version: 9.0.0-dev+v8.0.0-14872-gd3c57bc97
Revision: v8.0.0-14872-gd3c57bc97
Compiled: 2026-01-15T16:57:17
Compiler: GNU 11.4.0 on Linux-6.8.0-87-generic x86_64
Build Info: release IPO VTR_ASSERT_LEVEL=2

University of Toronto
verilogtorouting.org
vtr-users@googlegroups.com
This is free open source code under MIT license.

VPR was run with the following command-line:
vpr /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run065/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_tileable_40nm.xml mult4.blif --clock_modeling route --device 2x2 --route_chan_width 20 --skip_sync_clustering_and_routing_results on

Using up to 1 parallel worker(s)

Architecture file: /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run065/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_tileable_40nm.xml
Circuit name: mult4

# Loading Architecture Description
Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 3: Model 'frac_lut6' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 4: Model 'frac_lut6' output port 'lut6_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 5: Model 'frac_lut6' output port 'lut5_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
mode 'io[physical]' is defined by user to be disabled in packing
mode 'fle[physical]' is defined by user to be disabled in packing
mode 'fabric[default]' is defined by user to be disabled in packing
mode 'frac_logic[default]' is defined by user to be disabled in packing
# Loading Architecture Description took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)

Timing analysis: ON
Circuit netlist file: mult4.net
Circuit placement file: mult4.place
Circuit routing file: mult4.route
Circuit SDC file: mult4.sdc
Vpr floorplanning constraints file: not specified

Packer: ENABLED
Placer: ENABLED
Analytical Placer: DISABLED
Router: ENABLED
Analysis: SKIP IF PRIOR FAIL

VPR was run with the following options:

NetlistOpts.absorb_buffer_luts            : true
NetlistOpts.sweep_dangling_primary_ios    : true
NetlistOpts.sweep_dangling_nets           : true
NetlistOpts.sweep_dangling_blocks         : true
NetlistOpts.sweep_constant_primary_outputs: false
NetlistOpts.netlist_verbosity             : 1
NetlistOpts.const_gen_inference           : COMB_SEQ

PackerOpts.allow_unrelated_clustering: auto
PackerOpts.timing_gain_weight: 0.750000
PackerOpts.connection_gain_weight: 0.900000
PackerOpts.cluster_seed_type: BLEND2
PackerOpts.connection_driven: true
PackerOpts.timing_driven: true
PackerOpts.target_external_pin_util: auto

PlacerOpts.place_freq: PLACE_ONCE
PlacerOpts.place_algorithm: CRITICALITY_TIMING_PLACE
PlacerOpts.pad_loc_type: FREE
PlacerOpts.constraints_file: No constraints file given
PlacerOpts.place_chan_width: 20
PlacerOpts.inner_loop_recompute_divider: 0
PlacerOpts.recompute_crit_iter: 1
PlacerOpts.timing_tradeoff: 0.500000
PlacerOpts.td_place_exp_first: 1.000000
PlacerOpts.td_place_exp_last: 8.000000
PlacerOpts.delay_offset: 0.000000
PlacerOpts.delay_ramp_delta_threshold: -1
PlacerOpts.delay_ramp_slope: 0.000000
PlacerOpts.tsu_rel_margin: 1.000000
PlacerOpts.tsu_abs_margin: 0.000000
PlacerOpts.post_place_timing_report_file: 
PlacerOpts.allowed_tiles_for_delay_model: 
PlacerOpts.delay_model_reducer: MIN
PlacerOpts.delay_model_type: SIMPLE
PlacerOpts.rlim_escape_fraction: 0.000000
PlacerOpts.move_stats_file: 
PlacerOpts.placement_saves_per_temperature: 0
PlacerOpts.effort_scaling: CIRCUIT
PlacerOpts.place_delta_delay_matrix_calculation_method: ASTAR_ROUTE
PlaceOpts.seed: 1
AnnealSched.type: AUTO_SCHED
AnnealSched.inner_num: 0.500000

RouterOpts.route_type: DETAILED
RouterOpts.flat_routing: false
RouterOpts.choke_points: on
RouterOpts.router_algorithm: TIMING_DRIVEN
RouterOpts.base_cost_type: DELAY_NORMALIZED_LENGTH
RouterOpts.fixed_channel_width: 20
RouterOpts.check_route: FULL
RouterOpts.acc_fac: 1.000000
RouterOpts.bb_factor: 3
RouterOpts.bend_cost: 0.000000
RouterOpts.first_iter_pres_fac: 0.000000
RouterOpts.initial_pres_fac: 0.500000
RouterOpts.pres_fac_mult: 1.300000
RouterOpts.max_pres_fac: 1000.000000
RouterOpts.max_router_iterations: 50
RouterOpts.min_incremental_reroute_fanout: 16
RouterOpts.initial_acc_cost_chan_congestion_threshold: 0.500000
RouterOpts.initial_acc_cost_chan_congestion_weight: 0.500000
RouterOpts.do_check_rr_graph: true
RouterOpts.verify_binary_search: false
RouterOpts.min_channel_width_hint: 0
RouterOpts.read_rr_edge_metadata: false
RouterOpts.exit_after_first_routing_iteration: false
RouterOpts.astar_fac: 1.200000
RouterOpts.astar_offset: 0.000000
RouterOpts.router_profiler_astar_fac: 1.200000
RouterOpts.enable_parallel_connection_router: false
RouterOpts.post_target_prune_fac: 1.200000
RouterOpts.post_target_prune_offset: 0
RouterOpts.multi_queue_num_threads: 1
RouterOpts.multi_queue_num_queues: 2
RouterOpts.multi_queue_direct_draining: false
RouterOpts.criticality_exp: 1.000000
RouterOpts.max_criticality: 0.990000
RouterOpts.init_wirelength_abort_threshold: 0.850000
RouterOpts.incr_reroute_delay_ripup: AUTO
RouterOpts.save_routing_per_iteration: false
RouterOpts.congested_routing_iteration_threshold_frac: 1.000000
RouterOpts.high_fanout_threshold: 64
RouterOpts.router_debug_net: -2
RouterOpts.router_debug_sink_rr: -2
RouterOpts.router_debug_iteration: -2
RouterOpts.max_convergence_count: 1
RouterOpts.reconvergence_cpd_threshold: 0.990000
RouterOpts.update_lower_bound_delays: true
RouterOpts.first_iteration_timing_report_file: 
RouterOpts.route_bb_update: DYNAMIC
RouterOpts.lookahead_type: MAP
RouterOpts.initial_timing: LOOKAHEAD
RouterOpts.router_heap: FOUR_ARY_HEAP
RouterOpts.routing_failure_predictor = SAFE
RouterOpts.routing_budgets_algorithm = DISABLE

AnalysisOpts.gen_post_synthesis_netlist: false
AnalysisOpts.gen_post_implementation_merged_netlist: false
AnalysisOpts.gen_post_implementation_sdc: false
AnalysisOpts.timing_report_npaths: 100
AnalysisOpts.timing_report_skew: false
AnalysisOpts.echo_dot_timing_graph_node: -1
AnalysisOpts.timing_report_detail: NETLIST
AnalysisOpts.post_synth_netlist_unconn_input_handling: UNCONNECTED
AnalysisOpts.post_synth_netlist_unconn_output_handling: UNCONNECTED
AnalysisOpts.post_synth_netlist_module_parameters: on

# Building complex block graph
# Building complex block graph took 0.01 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
Circuit file: mult4.blif
# Load circuit
# Load circuit took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
# Clean circuit
Absorbed 0 LUT buffers
Inferred    0 additional primitive pins as constant generators since they have no combinationally connected inputs
Inferred    0 additional primitive pins as constant generators due to constant inputs
Swept input(s)      : 0
Swept output(s)     : 0 (0 dangling, 0 constant)
Swept net(s)        : 0
Swept block(s)      : 0
Constant Pins Marked: 0
# Clean circuit took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
# Compress circuit
# Compress circuit took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
# Verify circuit
# Verify circuit took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
Circuit Statistics:
  Blocks: 37
    .input :       8
    .names :      21
        2-LUT:       3
        3-LUT:       1
        4-LUT:       4
        5-LUT:       3
        6-LUT:      10
    .output:       8
  Nets  : 29
    Avg Fanout:     3.7
    Max Fanout:     9.0
    Min Fanout:     1.0
  Netlist Clocks: 0
# Build Timing Graph
  Timing Graph Nodes: 137
  Timing Graph Edges: 208
  Timing Graph Levels: 8
# Build Timing Graph took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
Netlist contains 0 clocks
# Load Timing Constraints

SDC file 'mult4.sdc' not found
Setting default timing constraints:
   * constrain all primary inputs and primary outputs on a virtual external clock 'virtual_io_clock'
   * optimize virtual clock to run as fast as possible
Timing constraints created 1 clocks
  Constrained Clock 'virtual_io_clock' (Virtual Clock)

# Load Timing Constraints took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
# Packing
## Prepacker
## Prepacker took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
## Initializing Pre-Cluster Timing
Using inter-cluster delay: 1.33777e-09
## Initializing Pre-Cluster Timing took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
Begin packing 'mult4.blif'.

After removing unused inputs...
	total blocks: 37, total nets: 29, total inputs: 8, total outputs: 8
Packing with pin utilization targets: io:1,1 clb:0.8,0.6
Packing with high fanout thresholds: io:128 clb:32
Starting Clustering - Clustering Progress: 
-------------------   --------------------------   ---------
Molecules processed   Number of clusters created   FPGA size
-------------------   --------------------------   ---------
    14/37       37%                            1     4 x 4     
    21/37       56%                            2     4 x 4     
    22/37       59%                            3     4 x 4     
    23/37       62%                            4     4 x 4     
    24/37       64%                            5     4 x 4     
    25/37       67%                            6     4 x 4     
    26/37       70%                            7     4 x 4     
    27/37       72%                            8     4 x 4     
    28/37       75%                            9     4 x 4     
    29/37       78%                           10     4 x 4     
    30/37       81%                           11     4 x 4     
    31/37       83%                           12     4 x 4     
    32/37       86%                           13     4 x 4     
    33/37       89%                           14     4 x 4     
    34/37       91%                           15     4 x 4     
    35/37       94%                           16     4 x 4     
    36/37       97%                           17     4 x 4     
    37/37      100%                           18     4 x 4     

Logic Element (fle) detailed count:
  Total number of Logic Elements used : 17
  LEs used for logic and registers    : 0
  LEs used for logic only             : 17
  LEs used for registers only         : 0

FPGA sized to 4 x 4 (2x2)
Device Utilization: 0.25 (target 1.00)
	Block Utilization: 0.25 Type: io
	Block Utilization: 0.50 Type: clb

Final Clustering Statistics: 
----------   --------   ------------------------------------   --------------------------
Block Type   # Blocks   Avg. # of input clocks and pins used   Avg. # of output pins used
----------   --------   ------------------------------------   --------------------------
     EMPTY          0                                      0                            0   
        io         16                                    0.5                          0.5   
       clb          2                                     13                            9   
Absorbed logical nets 3 out of 29 nets, 26 nets not absorbed.

Netlist conversion complete.

Incr Slack updates 1 in 1.062e-06 sec
Full Max Req/Worst Slack updates 1 in 4.4e-06 sec
Incr Max Req/Worst Slack updates 0 in 0 sec
Incr Criticality updates 0 in 0 sec
Full Criticality updates 1 in 2.121e-06 sec
# Packing took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
# Load packing
## Loading packed FPGA netlist file.
Netlist generated from file 'mult4.net'.
Detected 0 constant generators (to see names run with higher pack verbosity)
## Loading packed FPGA netlist file. took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
Warning 6: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
Completed clustering consistency check successfully.
Cluster level netlist and block usage statistics
Netlist num_nets: 26
Netlist num_blocks: 18
Netlist EMPTY blocks: 0.
Netlist io blocks: 16.
Netlist clb blocks: 2.
Netlist inputs pins: 8
Netlist output pins: 8

Pb types usage...
  io             : 16
   inpad         : 8
   outpad        : 8
  clb            : 2
   fle           : 17
    lut5inter    : 7
     ble5        : 11
      lut5       : 11
       lut       : 11
    ble6         : 10
     lut6        : 10
      lut        : 10

# Load packing took 0.03 seconds (max_rss 64.6 MiB, delta_rss +34.6 MiB)
# Create Device
## Build Device Grid
FPGA sized to 4 x 4: 16 grid tiles (2x2)
## Build Device Grid took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph
X-direction routing channel width is 20
Y-direction routing channel width is 20
### Build RR Graph Edges
### Build RR Graph Edges took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
  RR Graph Nodes: 744
  RR Graph Edges: 1732
# Create Device took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Resource usage...
	Netlist
		16	blocks of type: io
	Architecture
		64	blocks of type: io
	Netlist
		2	blocks of type: clb
	Architecture
		4	blocks of type: clb

Device Utilization: 0.25 (target 1.00)
	Physical Tile io:
	Block Utilization: 0.25 Logical Block: io
	Physical Tile clb:
	Block Utilization: 0.50 Logical Block: clb


# Computing router lookahead map
## Computing wire lookahead
## Computing wire lookahead took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
## Computing src/opin lookahead
## Computing src/opin lookahead took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Computing router lookahead map took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Compressed grid construction
# Compressed grid construction took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Bounding box mode is Cube

# Computing placement delta delay look-up
RR graph channel widths unchanged, skipping RR graph rebuild
Serial Connection Router is being destroyed. Time spent on path search: 0.000 seconds.
# Computing placement delta delay look-up took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Placement
## Initial Placement
Initial placement iteration 0 has finished successfully
## Initial Placement took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Using simple RL 'Softmax agent' for choosing move and block types

Completed placement consistency check successfully.
Initial placement cost: 1 bb_cost: 5.30935 td_cost: 6.47339e-09
Initial placement BB estimate of wirelength: 98
Initial placement estimated Critical Path Delay (CPD): 2.07439 ns
Initial placement estimated setup Total Negative Slack (sTNS): -11.6502 ns
Initial placement estimated setup Worst Negative Slack (sWNS): -2.07439 ns

Initial placement estimated setup slack histogram:
[ -2.1e-09:   -2e-09) 1 ( 12.5%) |****************
[   -2e-09: -1.8e-09) 0 (  0.0%) |
[ -1.8e-09: -1.7e-09) 2 ( 25.0%) |*********************************
[ -1.7e-09: -1.6e-09) 0 (  0.0%) |
[ -1.6e-09: -1.5e-09) 2 ( 25.0%) |*********************************
[ -1.5e-09: -1.4e-09) 0 (  0.0%) |
[ -1.4e-09: -1.2e-09) 0 (  0.0%) |
[ -1.2e-09: -1.1e-09) 0 (  0.0%) |
[ -1.1e-09:   -1e-09) 0 (  0.0%) |
[   -1e-09: -8.9e-10) 3 ( 37.5%) |*************************************************
Placement contains 0 placement macros involving 0 blocks (average macro size -nan)

Moves per temperature: 23

---- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
Tnum   Time       T Av Cost Av BB Cost Av TD Cost     CPD       sTNS     sWNS Ac Rate Std Dev  R lim Crit Exp Tot Moves  Alpha
      (sec)                                          (ns)       (ns)     (ns)                                                 
---- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
   1    0.0 6.1e-03   0.999       5.14 6.4215e-09   2.074      -11.7   -2.074   0.696  0.0061    3.0     1.00        23  1.000
   2    0.0 5.8e-03   0.997       5.05 6.3206e-09   2.074      -11.3   -2.074   0.696  0.0051    3.0     1.00        46  0.950
   3    0.0 5.5e-03   1.012       5.15 6.34e-09     2.074      -11.3   -2.074   0.478  0.0081    3.0     1.00        69  0.950
   4    0.0 5.3e-03   0.981       5.10 6.3132e-09   2.098      -11.6   -2.098   0.522  0.0035    3.0     1.00        92  0.950
   5    0.0 5.0e-03   0.992       4.93 6.3449e-09   2.074      -11.3   -2.074   0.261  0.0045    3.0     1.00       115  0.950
   6    0.0 4.7e-03   0.984       4.80 4.9649e-09   2.074      -11.3   -2.074   0.304  0.0038    2.5     2.88       138  0.950
   7    0.0 4.5e-03   1.014       4.85 4.5973e-09   2.074      -11.6   -2.074   0.565  0.0105    2.1     4.05       161  0.950
   8    0.0 4.3e-03   1.005       5.01 5.0687e-09   2.098      -11.7   -2.098   0.391  0.0077    2.4     3.12       184  0.950
   9    0.0 4.1e-03   0.989       5.00 4.5274e-09   2.169      -11.8   -2.169   0.522  0.0109    2.3     3.53       207  0.950
  10    0.0 3.9e-03   0.979       4.79 4.6982e-09   2.169      -11.8   -2.169   0.391  0.0090    2.5     2.87       230  0.950
  11    0.0 3.7e-03   1.011       4.88 4.7736e-09   2.074      -11.3   -2.074   0.348  0.0068    2.3     3.29       253  0.950
  12    0.0 3.5e-03   0.996       4.92 4.4879e-09   2.074      -11.3   -2.074   0.435  0.0055    2.1     4.05       276  0.950
  13    0.0 3.3e-03   0.999       4.82 4.4713e-09   2.074      -11.3   -2.074   0.348  0.0002    2.1     4.09       299  0.950
  14    0.0 3.1e-03   0.997       4.80 4.2635e-09   2.074      -11.3   -2.074   0.348  0.0031    1.9     4.77       322  0.950
  15    0.0 3.0e-03   1.006       4.90 4.1033e-09   2.074      -11.3   -2.074   0.522  0.0041    1.7     5.39       345  0.950
  16    0.0 2.8e-03   0.997       4.90 4.2303e-09   2.074      -11.3   -2.074   0.261  0.0014    1.9     4.89       368  0.950
  17    0.0 2.7e-03   0.999       4.91 3.9513e-09   2.074      -11.3   -2.074   0.478  0.0027    1.5     6.08       391  0.950
  18    0.0 2.6e-03   0.992       4.81 3.995e-09    2.074      -11.3   -2.074   0.478  0.0050    1.6     5.87       414  0.950
  19    0.0 2.4e-03   1.002       4.78 4.0425e-09   2.074      -11.3   -2.074   0.261  0.0031    1.7     5.65       437  0.950
  20    0.0 2.3e-03   1.002       4.86 3.8312e-09   2.074      -11.3   -2.074   0.391  0.0034    1.4     6.70       460  0.950
  21    0.0 2.2e-03   0.997       4.85 3.7898e-09   2.074      -11.3   -2.074   0.348  0.0045    1.3     6.93       483  0.950
  22    0.0 2.1e-03   0.990       4.74 3.7203e-09   2.074      -11.3   -2.074   0.304  0.0044    1.2     7.36       506  0.950
  23    0.0 2.0e-03   0.999       4.69 3.6359e-09   2.074      -11.3   -2.074   0.174  0.0014    1.0     7.92       529  0.950
  24    0.0 1.9e-03   1.004       4.70 3.6242e-09   2.074      -11.3   -2.074   0.391  0.0024    1.0     8.00       552  0.950
  25    0.0 1.8e-03   1.000       4.72 3.6242e-09   2.074      -11.3   -2.074   0.304  0.0000    1.0     8.00       575  0.950
  26    0.0 1.7e-03   1.000       4.72 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0000    1.0     8.00       598  0.950
  27    0.0 1.6e-03   0.998       4.70 3.6242e-09   2.074      -11.3   -2.074   0.435  0.0011    1.0     8.00       621  0.950
  28    0.0 1.5e-03   1.005       4.77 3.6242e-09   2.074      -11.3   -2.074   0.130  0.0029    1.0     8.00       644  0.950
Agent's 2nd state: 
  29    0.0 1.2e-03   0.998       4.74 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0038    1.0     8.00       667  0.800
Checkpoint saved: bb_costs=4.68206, TD costs=3.62421e-09, CPD=  2.074 (ns) 
  30    0.0 1.2e-03   1.000       4.68 3.6242e-09   2.074      -11.3   -2.074   0.304  0.0011    1.0     8.00       690  0.950
  31    0.0 1.1e-03   1.000       4.66 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0000    1.0     8.00       713  0.950
  32    0.0 1.1e-03   1.000       4.66 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       736  0.950
  33    0.0 8.4e-04   1.000       4.66 3.6242e-09   2.074      -11.3   -2.074   0.043  0.0000    1.0     8.00       759  0.800
  34    0.0 6.7e-04   0.998       4.64 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0014    1.0     8.00       782  0.800
  35    0.0 6.4e-04   1.000       4.65 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       805  0.950
  36    0.0 5.1e-04   1.000       4.65 3.6242e-09   2.074      -11.3   -2.074   0.217  0.0011    1.0     8.00       828  0.800
  37    0.0 4.9e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0003    1.0     8.00       851  0.950
  38    0.0 4.6e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       874  0.950
  39    0.0 3.7e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0000    1.0     8.00       897  0.800
  40    0.0 3.5e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       920  0.950
  41    0.0 2.8e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.130  0.0000    1.0     8.00       943  0.800
  42    0.0 2.2e-04   0.997       4.60 3.6242e-09   2.074      -11.3   -2.074   0.217  0.0000    1.0     8.00       966  0.800
  43    0.0 2.1e-04   1.000       4.60 3.6242e-09   2.074      -11.3   -2.074   0.043  0.0000    1.0     8.00       989  0.950
  44    0.0 0.0e+00   1.000       4.60 3.6242e-09   2.074      -11.3   -2.074   0.130  0.0000    1.0     8.00      1012  0.800
## Placement Quench took 0.00 seconds (max_rss 64.6 MiB)
post-quench CPD = 2.07439 (ns) 

Completed placement consistency check successfully.

Swaps called: 1030

Aborted Move Reasons:
  No moves aborted

BB estimate of min-dist (placement) wire length: 86

Placement estimated critical path delay (least slack): 2.07439 ns, Fmax: 482.069 MHz
Placement estimated setup Worst Negative Slack (sWNS): -2.07439 ns
Placement estimated setup Total Negative Slack (sTNS): -11.3066 ns

Placement estimated setup slack histogram:
[ -2.1e-09:   -2e-09) 1 ( 12.5%) |****************
[   -2e-09: -1.8e-09) 0 (  0.0%) |
[ -1.8e-09: -1.7e-09) 2 ( 25.0%) |*********************************
[ -1.7e-09: -1.6e-09) 0 (  0.0%) |
[ -1.6e-09: -1.5e-09) 2 ( 25.0%) |*********************************
[ -1.5e-09: -1.3e-09) 0 (  0.0%) |
[ -1.3e-09: -1.2e-09) 0 (  0.0%) |
[ -1.2e-09: -1.1e-09) 0 (  0.0%) |
[ -1.1e-09: -9.8e-10) 0 (  0.0%) |
[ -9.8e-10: -8.6e-10) 3 ( 37.5%) |*************************************************

Placement estimated geomean non-virtual intra-domain period: nan ns (nan MHz)
Placement estimated fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz)

Placement cost: 1, bb_cost: 4.5957, td_cost: 3.62421e-09, 

Placement resource usage:
  io  implemented as io : 16
  clb implemented as clb: 2

Placement number of temperatures: 44
Placement total # of swap attempts: 1030
	Swaps accepted:  311 (30.2 %)
	Swaps rejected:  719 (69.8 %)
	Swaps aborted:    0 ( 0.0 %)


Placement perturbation distribution by block and move type: 
------------------ ----------------- ---------------- ---------------- --------------- ------------ 
    Block Type         Move Type       (%) of Total      Accepted(%)     Rejected(%)    Aborted(%)
------------------ ----------------- ---------------- ---------------- --------------- ------------ 
io                 Uniform                24.08            35.48           64.52          0.00         
                   Median                 17.86            28.80           71.20          0.00         
                   Centroid               16.60            39.18           60.82          0.00         
                   W. Centroid            21.07            38.71           61.29          0.00         
                   W. Median              3.40             11.43           88.57          0.00         
                   Crit. Uniform          1.84             21.05           78.95          0.00         
                   Feasible Region        2.62             37.04           62.96          0.00         

clb                Uniform                2.04             0.00            100.00         0.00         
                   Median                 1.17             8.33            91.67          0.00         
                   Centroid               2.04             0.00            100.00         0.00         
                   W. Centroid            1.75             0.00            100.00         0.00         
                   W. Median              0.78             0.00            100.00         0.00         
                   Crit. Uniform          1.84             0.00            100.00         0.00         
                   Feasible Region        2.91             0.00            100.00         0.00         


Placement Quench timing analysis took 3.021e-05 seconds (2.6935e-05 STA, 3.275e-06 slack) (1 full updates: 1 setup, 0 hold, 0 combined).
Placement Total  timing analysis took 0.0016526 seconds (0.00149416 STA, 0.000158442 slack) (46 full updates: 46 setup, 0 hold, 0 combined).
update_td_costs: connections 0 nets 0 sum_nets 0 total 0
# Placement took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

# Routing
RR graph channel widths unchanged, skipping RR graph rebuild
## Initializing router criticalities
Initial Net Connection Criticality Histogram:
[        0:      0.1)  0 (  0.0%) |
[      0.1:      0.2)  0 (  0.0%) |
[      0.2:      0.3)  0 (  0.0%) |
[      0.3:      0.4)  0 (  0.0%) |
[      0.4:      0.5)  5 ( 14.7%) |********************
[      0.5:      0.6)  0 (  0.0%) |
[      0.6:      0.7)  0 (  0.0%) |
[      0.7:      0.8)  7 ( 20.6%) |****************************
[      0.8:      0.9) 10 ( 29.4%) |****************************************
[      0.9:        1) 12 ( 35.3%) |************************************************
## Initializing router criticalities took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
Iter   Time    pres  BBs    Heap  Re-Rtd  Re-Rtd Overused RR Nodes      Wirelength      CPD       sTNS       sWNS       hTNS       hWNS Est Succ
      (sec)     fac Updt    push    Nets   Conns                                       (ns)       (ns)       (ns)       (ns)       (ns)     Iter
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
   1    0.0     0.0    0     622      26      34      25 ( 3.360%)     103 (42.9%)    2.473     -13.88     -2.473      0.000      0.000      N/A
Incr Slack updates 46 in 3.3812e-05 sec
Full Max Req/Worst Slack updates 3 in 2.883e-06 sec
Incr Max Req/Worst Slack updates 43 in 1.7934e-05 sec
Incr Criticality updates 40 in 7.1615e-05 sec
Full Criticality updates 6 in 1.2213e-05 sec
   2    0.0     0.5    0     514      20      27      17 ( 2.285%)     102 (42.5%)    2.473     -13.82     -2.473      0.000      0.000      N/A
   3    0.0     0.6    0     455      13      17      19 ( 2.554%)     110 (45.8%)    2.473     -14.19     -2.473      0.000      0.000      N/A
   4    0.0     0.8    0     472      14      19      15 ( 2.016%)     110 (45.8%)    2.473     -14.18     -2.473      0.000      0.000      N/A
   5    0.0     1.1    0     471      13      18      13 ( 1.747%)     116 (48.3%)    2.473     -14.42     -2.473      0.000      0.000      N/A
   6    0.0     1.4    0     354      13      19      13 ( 1.747%)     120 (50.0%)    2.473     -14.50     -2.473      0.000      0.000      N/A
   7    0.0     1.9    0     430      13      19      11 ( 1.478%)     121 (50.4%)    2.473     -14.63     -2.473      0.000      0.000      N/A
   8    0.0     2.4    0     380      12      17      10 ( 1.344%)     115 (47.9%)    2.473     -14.38     -2.473      0.000      0.000      N/A
   9    0.0     3.1    0     275       9      13       3 ( 0.403%)     128 (53.3%)    2.471     -15.09     -2.471      0.000      0.000      N/A
  10    0.0     4.1    0     209       5       7       2 ( 0.269%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       14
  11    0.0     5.3    0     192       5       7       3 ( 0.403%)     129 (53.8%)    2.471     -15.25     -2.471      0.000      0.000       12
  12    0.0     6.9    0     176       4       6       2 ( 0.269%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       13
  13    0.0     9.0    0     246       6       8       3 ( 0.403%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       13
  14    0.0    11.6    0     197       4       5       3 ( 0.403%)     122 (50.8%)    2.471     -14.85     -2.471      0.000      0.000       15
  15    0.0    15.1    0     173       3       4       2 ( 0.269%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       20
  16    0.0    19.7    0     388       6       8       4 ( 0.538%)     147 (61.2%)    2.471     -16.00     -2.471      0.000      0.000       20
  17    0.0    25.6    0     153       5       6       2 ( 0.269%)     133 (55.4%)    2.526     -15.50     -2.526      0.000      0.000      inf
  18    0.0    33.3    0     106       5       7       1 ( 0.134%)     137 (57.1%)    2.645     -15.62     -2.645      0.000      0.000      inf
  19    0.0    43.3    0     108       5       7       2 ( 0.269%)     133 (55.4%)    2.663     -15.63     -2.663      0.000      0.000       31
  20    0.0    56.2    0     108       4       6       1 ( 0.134%)     133 (55.4%)    2.529     -15.51     -2.529      0.000      0.000       33
  21    0.0    73.1    0     219       5       7       2 ( 0.269%)     138 (57.5%)    2.529     -15.83     -2.529      0.000      0.000       23
  22    0.0    95.0    0      84       3       5       1 ( 0.134%)     133 (55.4%)    2.529     -15.51     -2.529      0.000      0.000       26
  23    0.0   123.5    0     128       4       6       1 ( 0.134%)     134 (55.8%)    2.665     -15.64     -2.665      0.000      0.000       24
  24    0.0   160.6    0     148       4       6       1 ( 0.134%)     134 (55.8%)    2.665     -15.64     -2.665      0.000      0.000       24
  25    0.0   208.8    0     146       4       6       3 ( 0.403%)     139 (57.9%)    2.935     -15.91     -2.935      0.000      0.000       23
  26    0.0   271.4    0     112       4       6       1 ( 0.134%)     133 (55.4%)    2.529     -15.51     -2.529      0.000      0.000       27
  27    0.0   352.8    0     213       5       7       2 ( 0.269%)     141 (58.7%)    3.031     -16.01     -3.031      0.000      0.000       27
  28    0.0   458.7    0     181       4       6       1 ( 0.134%)     134 (55.8%)    2.665     -15.64     -2.665      0.000      0.000       31
  29    0.0   596.3    0     140       4       6       2 ( 0.269%)     142 (59.2%)    3.165     -16.14     -3.165      0.000      0.000       31
  30    0.0   775.1    0     133       4       6       3 ( 0.403%)     143 (59.6%)    3.165     -16.30     -3.165      0.000      0.000       38
  31    0.0  1000.0    0     192       6       9       2 ( 0.269%)     151 (62.9%)    2.935     -16.69     -2.935      0.000      0.000      132
  32    0.0  1000.0    0     196       6       8       3 ( 0.403%)     152 (63.3%)    3.009     -16.97     -3.009      0.000      0.000      inf
  33    0.0  1000.0    0     204       5       7       1 ( 0.134%)     141 (58.7%)    2.935     -16.15     -2.935      0.000      0.000       12
  34    0.0  1000.0    0     210       5       7       0 ( 0.000%)     145 (60.4%)    2.935     -16.34     -2.935      0.000      0.000        5
Restoring best routing
Critical path: 2.93509 ns
Successfully routed after 34 routing iterations.
Final Net Connection Criticality Histogram:
[        0:      0.1)  0 (  0.0%) |
[      0.1:      0.2)  0 (  0.0%) |
[      0.2:      0.3)  0 (  0.0%) |
[      0.3:      0.4)  1 (  2.9%) |***
[      0.4:      0.5)  2 (  5.9%) |******
[      0.5:      0.6)  3 (  8.8%) |*********
[      0.6:      0.7)  1 (  2.9%) |***
[      0.7:      0.8)  5 ( 14.7%) |***************
[      0.8:      0.9)  6 ( 17.6%) |******************
[      0.9:        1) 16 ( 47.1%) |************************************************
Router Stats: total_nets_routed: 248 total_connections_routed: 346 total_heap_pushes: 8335 total_heap_pops: 5679 
Serial Connection Router is being destroyed. Time spent on path search: 0.000 seconds.
# Routing took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Checking to ensure routing is legal...
# Checking to ensure non-configurable edges are legal
# Checking to ensure non-configurable edges are legal took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Completed routing consistency check successfully.

Serial number (magic cookie) for the routing is: -1300952
Circuit successfully routed with a channel width factor of 20.
Warning 7: Synchronization between packing and routing results was not applied due to skip_sync_clustering_and_routing_results being set to true
Final Clustering Statistics: 
----------   --------   ------------------------------------   --------------------------
Block Type   # Blocks   Avg. # of input clocks and pins used   Avg. # of output pins used
----------   --------   ------------------------------------   --------------------------
     EMPTY          0                                      0                            0   
        io         16                                    0.5                          0.5   
       clb          2                                     13                            9   
Absorbed logical nets 3 out of 29 nets, 26 nets not absorbed.


Average number of bends per net: 2.50000  Maximum # of bends: 14

Number of global nets: 0
Number of routed nets (nonglobal): 26
Wire length results (in units of 1 clb segments)...
	Total wirelength: 145, average net length: 5.57692
	Maximum net length: 23

Wire length results in terms of physical segments...
	Total wiring segments used: 94, average wire segments per net: 3.61538
	Maximum segments used by a net: 15
	Total local nets with reserved CLB opins: 0
Total number of nets absorbed: 0

Routing channel utilization histogram:
[        1:      inf) 0 (  0.0%) |
[      0.9:        1) 0 (  0.0%) |
[      0.8:      0.9) 0 (  0.0%) |
[      0.7:      0.8) 5 ( 27.8%) |*****************************************
[      0.5:      0.6) 6 ( 33.3%) |*************************************************
[      0.4:      0.5) 0 (  0.0%) |
[      0.3:      0.4) 1 (  5.6%) |********
[      0.2:      0.3) 0 (  0.0%) |
[      0.1:      0.2) 0 (  0.0%) |
[        0:      0.1) 6 ( 33.3%) |*************************************************
Maximum routing channel utilization:      0.75 at (2,0)

X - Directed channels: layer   y   max occ   ave occ   ave cap
                        ----- ---- -------- -------- --------
                            0    0       15   13.500       20
                            0    1       13   13.000       20
                            0    2       13   12.500       20
Y - Directed channels: layer   x   max occ   ave occ   ave cap
                        ----- ---- -------- -------- --------
                            0    0       12   11.500       20
                            0    1       11    9.500       20
                            0    2       13   12.500       20

Total existing wires segments: CHANX 78, CHANY 67, ALL 145
Total used wires segments:     CHANX 78, CHANY 67, ALL 145
Usage percentage:               CHANX 0%, CHANY -1%, ALL -850310905%

Logic area (in minimum width transistor areas, excludes I/Os and empty grid tiles)...
	Total logic block area (Warning, need to add pitch of routing to blocks with height > 3): 215576
	Total used logic block area: 107788

Routing area (in minimum width transistor areas)...
	Total routing area: 12917.9, per logic tile: 807.366

Total Number of Wiring Segments by Direction: direction length number
                                              --------- ------ -------
                                                      X      4     78
                                                      Y      4     78

X - Directed Wiring Segment usage by length: length utilization
                                             ------ -----------
                                             4       0.628

Y - Directed Wiring Segment usage by length: length utilization
                                             ------ -----------
                                             4       0.577

Segment occupancy by length: Length Occupancy Capacity Utilization
                             ------ --------- -------- -----------
                             L4            94      156       0.603

Segment occupancy by type: name type utilization
                           ---- ---- -----------
                             L4    0       0.603

Final hold Worst Negative Slack (hWNS): 0 ns
Final hold Total Negative Slack (hTNS): 0 ns

Final hold slack histogram:
[  8.3e-10:  9.5e-10) 3 ( 37.5%) |*************************************************
[  9.5e-10:  1.1e-09) 1 ( 12.5%) |****************
[  1.1e-09:  1.2e-09) 1 ( 12.5%) |****************
[  1.2e-09:  1.3e-09) 0 (  0.0%) |
[  1.3e-09:  1.4e-09) 2 ( 25.0%) |*********************************
[  1.4e-09:  1.5e-09) 0 (  0.0%) |
[  1.5e-09:  1.7e-09) 0 (  0.0%) |
[  1.7e-09:  1.8e-09) 0 (  0.0%) |
[  1.8e-09:  1.9e-09) 0 (  0.0%) |
[  1.9e-09:    2e-09) 1 ( 12.5%) |****************

Final critical path delay (least slack): 2.93509 ns, Fmax: 340.705 MHz
Final setup Worst Negative Slack (sWNS): -2.93509 ns
Final setup Total Negative Slack (sTNS): -16.3447 ns

Final setup slack histogram:
[ -2.9e-09: -2.8e-09) 1 ( 12.5%) |*************************
[ -2.8e-09: -2.6e-09) 1 ( 12.5%) |*************************
[ -2.6e-09: -2.4e-09) 0 (  0.0%) |
[ -2.4e-09: -2.3e-09) 1 ( 12.5%) |*************************
[ -2.3e-09: -2.1e-09) 0 (  0.0%) |
[ -2.1e-09: -1.9e-09) 2 ( 25.0%) |*************************************************
[ -1.9e-09: -1.8e-09) 0 (  0.0%) |
[ -1.8e-09: -1.6e-09) 1 ( 12.5%) |*************************
[ -1.6e-09: -1.4e-09) 0 (  0.0%) |
[ -1.4e-09: -1.3e-09) 2 ( 25.0%) |*************************************************

Final geomean non-virtual intra-domain period: nan ns (nan MHz)
Final fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz)

Incr Slack updates 1 in 1.191e-06 sec
Full Max Req/Worst Slack updates 1 in 9.2e-07 sec
Incr Max Req/Worst Slack updates 0 in 0 sec
Incr Criticality updates 0 in 0 sec
Full Criticality updates 1 in 2.332e-06 sec
Flow timing analysis took 0.00436041 seconds (0.00383856 STA, 0.000521851 slack) (83 full updates: 47 setup, 0 hold, 36 combined).
VPR succeeded
The entire flow of VPR took 0.06 seconds (max_rss 64.6 MiB)

Command line to execute: read_openfpga_arch -f /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run065/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_40nm_openfpga.xml

Confirm selected options when call command 'read_openfpga_arch':
--file, -f: /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run065/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_40nm_openfpga.xml
Reading XML architecture '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run065/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_40nm_openfpga.xml'...
Read OpenFPGA architecture
Warning 8: Automatically set circuit model 'frac_lut6' to be default in its type.
Warning 9: Automatically set circuit model 'DFFSRQ' to be default in its type.
Warning 10: Automatically set circuit model 'DFFR' to be default in its type.
Warning 11: Automatically set circuit model 'GPIO' to be default in its type.
Use the default configurable memory model 'DFFR' for circuit model 'mux_2level' port 'sram')
Use the default configurable memory model 'DFFR' for circuit model 'mux_2level_tapbuf' port 'sram')
Use the default configurable memory model 'DFFR' for circuit model 'mux_1level_tapbuf' port 'sram')
Use the default configurable memory model 'DFFR' for circuit model 'frac_lut6' port 'sram')
Read OpenFPGA architecture took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Check circuit library
Checking circuit library passed.
Check circuit library took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Found 0 errors when checking configurable memory circuit models!
Found 0 errors when checking configuration protocol!
Found 0 errors when checking tile annotation!

Command line to execute: read_openfpga_simulation_setting -f /home/moshida/OpenFPGA/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml

Confirm selected options when call command 'read_openfpga_simulation_setting':
--file, -f: /home/moshida/OpenFPGA/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Reading XML simulation setting '/home/moshida/OpenFPGA/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
Read OpenFPGA simulation settings
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: link_openfpga_arch --activity_file mult4_ace_out.act --sort_gsb_chan_node_in_edges

Confirm selected options when call command 'link_openfpga_arch':
--activity_file: mult4_ace_out.act
--sort_gsb_chan_node_in_edges: on
--verbose: off
Link OpenFPGA architecture to VPR architecture
# Build fast look-up for physical tile pins
# Build fast look-up for physical tile pins took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Building annotation for physical modes in pb_type...Done
Check physical mode annotation for pb_types passed.

Building annotation about physical types for pb_type interconnection...Done

Building annotation between operating and physical pb_types...Done
Check physical pb_type annotation for pb_types passed.

Building annotation between physical pb_types and circuit models...Done
Check physical pb_type annotation for circuit model passed.

Building annotation between physical pb_types and mode selection bits...Done
Check pb_type annotation for mode selection bits passed.
Assigning unique indices for primitive pb_graph nodes...Done
Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...Done
Check pb_graph annotation for physical nodes and pins passed.
Binded 2 routing resource graph switches to circuit models
Binded 1 routing segments to circuit models
Binded 0 direct connections to circuit models
# Annotating rr_node with routed nets
# Annotating rr_node with routed nets took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Loaded node-to-net mapping
Annotating previous nodes for rr_node...Warning 12: Override the previous node 'IPIN:467 side: (RIGHT,) (2,2,0)' by previous node 'IPIN:466 side: (RIGHT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 13: Override the previous node 'IPIN:466 side: (RIGHT,) (2,2,0)' by previous node 'IPIN:483 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 14: Override the previous node 'IPIN:245 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:249 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 15: Override the previous node 'IPIN:483 side: (LEFT,) (2,2,0)' by previous node 'IPIN:451 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 16: Override the previous node 'IPIN:249 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:261 side: (LEFT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 17: Override the previous node 'IPIN:261 side: (LEFT,) (2,1,0)' by previous node 'IPIN:223 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 18: Override the previous node 'IPIN:451 side: (TOP,) (2,2,0)' by previous node 'IPIN:452 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 19: Override the previous node 'IPIN:452 side: (TOP,) (2,2,0)' by previous node 'IPIN:489 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 20: Override the previous node 'IPIN:223 side: (TOP,) (2,1,0)' by previous node 'IPIN:224 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 21: Override the previous node 'IPIN:489 side: (LEFT,) (2,2,0)' by previous node 'IPIN:484 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 22: Override the previous node 'IPIN:224 side: (TOP,) (2,1,0)' by previous node 'IPIN:246 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 23: Override the previous node 'IPIN:484 side: (LEFT,) (2,2,0)' by previous node 'IPIN:454 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 24: Override the previous node 'IPIN:246 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:244 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 25: Override the previous node 'IPIN:454 side: (TOP,) (2,2,0)' by previous node 'IPIN:482 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 26: Override the previous node 'IPIN:244 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:243 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 27: Override the previous node 'IPIN:482 side: (LEFT,) (2,2,0)' by previous node 'IPIN:455 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 28: Override the previous node 'IPIN:243 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:226 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 29: Override the previous node 'IPIN:226 side: (TOP,) (2,1,0)' by previous node 'IPIN:233 side: (RIGHT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 30: Override the previous node 'IPIN:233 side: (RIGHT,) (2,1,0)' by previous node 'IPIN:221 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 31: Override the previous node 'IPIN:221 side: (TOP,) (2,1,0)' by previous node 'IPIN:222 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 32: Override the previous node 'IPIN:222 side: (TOP,) (2,1,0)' by previous node 'IPIN:254 side: (LEFT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 33: Override the previous node 'IPIN:254 side: (LEFT,) (2,1,0)' by previous node 'IPIN:235 side: (RIGHT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 34: Override the previous node 'IPIN:235 side: (RIGHT,) (2,1,0)' by previous node 'IPIN:230 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 35: Override the previous node 'IPIN:230 side: (TOP,) (2,1,0)' by previous node 'IPIN:236 side: (RIGHT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Done with 0 nodes mapping
Built 1732 incoming edges for routing resource graph
# Build General Switch Block(GSB) annotation on top of routing resource graph
[11%] Backannotated GSB[0][0]
[22%] Backannotated GSB[0][1]
[33%] Backannotated GSB[0][2]
[44%] Backannotated GSB[1][0]
[55%] Backannotated GSB[1][1]
[66%] Backannotated GSB[1][2]
[77%] Backannotated GSB[2][0]
[88%] Backannotated GSB[2][1]
[100%] Backannotated GSB[2][2]
Backannotated 9 General Switch Blocks (GSBs).
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
[11%] Sorted incoming edges for each routing track output node of GSB[0][0]
[22%] Sorted incoming edges for each routing track output node of GSB[0][1]
[33%] Sorted incoming edges for each routing track output node of GSB[0][2]
[44%] Sorted incoming edges for each routing track output node of GSB[1][0]
[55%] Sorted incoming edges for each routing track output node of GSB[1][1]
[66%] Sorted incoming edges for each routing track output node of GSB[1][2]
[77%] Sorted incoming edges for each routing track output node of GSB[2][0]
[88%] Sorted incoming edges for each routing track output node of GSB[2][1]
[100%] Sorted incoming edges for each routing track output node of GSB[2][2]
Sorted incoming edges for each routing track output node of 9 General Switch Blocks (GSBs).
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each input pin node of General Switch Block(GSB)
[11%] Sorted incoming edges for each input pin node of GSB[0][0]
[22%] Sorted incoming edges for each input pin node of GSB[0][1]
[33%] Sorted incoming edges for each input pin node of GSB[0][2]
[44%] Sorted incoming edges for each input pin node of GSB[1][0]
[55%] Sorted incoming edges for each input pin node of GSB[1][1]
[66%] Sorted incoming edges for each input pin node of GSB[1][2]
[77%] Sorted incoming edges for each input pin node of GSB[2][0]
[88%] Sorted incoming edges for each input pin node of GSB[2][1]
[100%] Sorted incoming edges for each input pin node of GSB[2][2]
Sorted incoming edges for each input pin node of 9 General Switch Blocks (GSBs).
# Sort incoming edges for each input pin node of General Switch Block(GSB) took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build a library of physical multiplexers
Built a multiplexer library of 12 physical multiplexers.
Maximum multiplexer size is 64.
	model 'mux_2level_tapbuf', input_size='5'
	model 'mux_2level_tapbuf', input_size='3'
	model 'mux_2level_tapbuf', input_size='4'
	model 'mux_2level_tapbuf', input_size='10'
	model 'mux_2level_tapbuf', input_size='8'
	model 'mux_2level_tapbuf', input_size='9'
	model 'mux_2level_tapbuf', input_size='12'
	model 'mux_2level_tapbuf', input_size='11'
	model 'mux_2level_tapbuf', input_size='6'
	model 'mux_2level', input_size='61'
	model 'mux_1level_tapbuf', input_size='3'
	model 'frac_lut6', input_size='64'
# Build a library of physical multiplexers took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build the annotation about direct connection between tiles
Built 0 tile-to-tile direct connections
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Building annotation for post-routing and clustering synchornization results...Done
Building annotation for mapped blocks on grid locations...Done
User specified the operating clock frequency to use VPR results
Use VPR critical path delay 3.52211e-18 [ns] with a 20 [%] slack in OpenFPGA.
Incr Slack updates 1 in 2.8825e-05 sec
Full Max Req/Worst Slack updates 1 in 1.776e-06 sec
Incr Max Req/Worst Slack updates 0 in 0 sec
Incr Criticality updates 0 in 0 sec
Full Criticality updates 1 in 3.907e-06 sec
Will apply operating clock frequency 283.921 [MHz] to simulations
User specified the number of operating clock cycles to be inferred from signal activities
Average net density: 0.08
Median net density: 0.00
Average net density after weighting: 0.13
Will apply 12 operating clock cycles to simulations
Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

Confirm selected options when call command 'check_netlist_naming_conflict':
--fix: on
--report: ./netlist_renaming.xml
Check naming violations of netlist blocks and nets
Fixed 66 naming conflicts in the netlist.
Naming fix-up report is generated to file './netlist_renaming.xml'
Check naming violations of netlist blocks and nets took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: build_fabric --compress_routing

Confirm selected options when call command 'build_fabric':
--frame_view: off
--compress_routing: on
--duplicate_grid_pin: off
--name_module_using_index: off
--load_fabric_key: off
--write_fabric_key: off
--group_tile: off
--group_config_block: off
--generate_random_fabric_key: off
--verbose: off
Identify unique General Switch Blocks (GSBs)
Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%)
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)


Build fabric module graph
# Build constant generator modules
# Build constant generator modules took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build user-defined modules
# Build user-defined modules took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build essential (inverter/buffer/logic gate) modules
# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build local encoder (for multiplexers) modules
# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Building multiplexer modules
# Building multiplexer modules took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build Look-Up Table (LUT) modules
# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build wire modules
# Build wire modules took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build memory modules
# Build memory modules took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build grid modules
Building logical tiles...Done
Building physical tiles...Done
# Build grid modules took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build unique routing modules...
# Build unique routing modules... took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build FPGA fabric module
## Add grid instances to top module
## Add grid instances to top module took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
## Add switch block instances to top module
## Add switch block instances to top module took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
## Add module nets between grids and GSBs
## Add module nets between grids and GSBs took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
## Add module nets for inter-tile connections
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
## Build configurable regions for the top module
## Build configurable regions for the top module took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
## Add module nets for configuration buses
## Add module nets for configuration buses took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
# Build FPGA fabric module took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Build fabric module graph took 0.01 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Create I/O location mapping for top module
Create I/O location mapping for top module took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Create global port info for top module
Create global port info for top module took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: repack --verbose

Confirm selected options when call command 'repack':
--design_constraints: off
--ignore_global_nets_on_pins: off
--verbose: on
Build routing resource graph for the physical implementation of logical tile
Building routing resource graph for logical tile 'io'...
	Number of nodes: 8
	Number of edges: 7
Check routing resource graph for logical tile passed
Building routing resource graph for logical tile 'clb'...
	Number of nodes: 574
	Number of edges: 4153
Check routing resource graph for logical tile passed
Done
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Repack clustered blocks to physical implementation of logical tile
Repack clustered block 'new_$abc$328$new_n22'...
Follow the same mapping results for net 'A[2]' on pin 'I[0]' during repacking (constrained net name is )
Pb route for Net A[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[0] -> clb[0].I[0]
Sink nodes:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[3]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[3]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[1]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[2]' during repacking (constrained net name is )
Follow the same mapping results for net 'new_$abc$328$new_n27' on pin 'I[3]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n27:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[3] -> clb[0].I[3]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[3]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[3]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[3]' on pin 'I[4]' during repacking (constrained net name is )
Pb route for Net A[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[4] -> clb[0].I[4]
Sink nodes:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[2]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[2]' on pin 'I[5]' during repacking (constrained net name is )
Pb route for Net B[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[5] -> clb[0].I[5]
Sink nodes:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[4]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[1]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[6]' during repacking (constrained net name is )
Pb route for Net A[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[6] -> clb[0].I[6]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[3]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[1]' on pin 'I[7]' during repacking (constrained net name is )
Pb route for Net A[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[7] -> clb[0].I[7]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[0]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[1]' on pin 'I[8]' during repacking (constrained net name is )
Pb route for Net B[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[8] -> clb[0].I[8]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[4]
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[0]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[0]' on pin 'I[9]' during repacking (constrained net name is )
Pb route for Net B[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[9] -> clb[0].I[9]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[1]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n25' on pin 'I[10]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n25:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[10] -> clb[0].I[10]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[3]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[3]' on pin 'I[11]' during repacking (constrained net name is )
Pb route for Net B[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[11] -> clb[0].I[11]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[1]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[1]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[12]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[13]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[14]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[15]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[16]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[17]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[18]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[19]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[20]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[21]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[22]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[23]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[24]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[25]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[26]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[27]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[28]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[29]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[30]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[31]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[32]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[33]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[34]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[35]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[36]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[37]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[38]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[39]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'clk[0]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n35:
Source node:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[0]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[3]
Pb route for Net new_$abc$328$new_n26:
Source node:
	clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[1]
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[0]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[3]
Pb route for Net Y[1]:
Source node:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[11]
Pb route for Net new_$abc$328$new_n30:
Source node:
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[2]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[1]
Pb route for Net new_$abc$328$new_n33:
Source node:
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[12]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[2]
Pb route for Net new_$abc$328$new_n32:
Source node:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[2]
Pb route for Net new_$abc$328$new_n36:
Source node:
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[13]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[5]
Pb route for Net Y[6]:
Source node:
	clb[0]/fle[4]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[4]
Pb route for Net new_$abc$328$new_n31:
Source node:
	clb[0]/fle[5]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[1]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[1]
Pb route for Net new_$abc$328$new_n24:
Source node:
	clb[0]/fle[6]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[6]
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[2]
Pb route for Net new_$abc$328$new_n23:
Source node:
	clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[7]
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[1]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[1]
Pb route for Net Y[5]:
Source node:
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[17]
Pb route for Net new_$abc$328$new_n29:
Source node:
	clb[0]/fle[8]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[0]
Pb route for Net new_$abc$328$new_n22:
Source node:
	clb[0]/fle[9]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[9]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[5]
Added 24 nets to be routed.
Reroute succeed
Update physical pb 'clb[0][default]/fle[0][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n35'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[0][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[1][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n26'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[1][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[1][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[1]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[1][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[2][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n30'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[2][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[2][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n33'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[2][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[3][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n32'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[3][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[3][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n36'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[3][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[4][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[6]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[4][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[5][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n31'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[5][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[6][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n24'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[6][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[7][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n23'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[7][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[7][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[5]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[7][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[8][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n29'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[8][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[9][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n22'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[9][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Save net 'A[2]' to physical pb_graph_pin 'clb[0].I[0]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[4]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[4]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0].I[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8].in[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0].I[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0].I[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0].I[6]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9].in[5]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[5]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0].I[7]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0].I[8]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[3]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[3]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0].I[9]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0].I[10]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8].in[4]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0].I[11]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0].out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0].O[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4].in[3]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1].out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0].O[1]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1].out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0].O[11]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2].out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0].O[2]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7].in[1]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2].out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0].O[12]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3].out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3].out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0].O[13]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4].in[5]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4].out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0].O[4]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5].out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2].in[1]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6].out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0].O[6]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7].out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0].O[7]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7].out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0].O[17]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8].out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7].in[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9].out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0].O[9]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8].in[5]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Saved results in physical pb
Done
Repack clustered block 'new_$abc$328$new_n25'...
Follow the same mapping results for net 'A[2]' on pin 'I[0]' during repacking (constrained net name is )
Pb route for Net A[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[0] -> clb[0].I[0]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[3]' on pin 'I[1]' during repacking (constrained net name is )
Pb route for Net A[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[1] -> clb[0].I[1]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[1]' on pin 'I[2]' during repacking (constrained net name is )
Pb route for Net A[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[2] -> clb[0].I[2]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n23' on pin 'I[3]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n23:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[3] -> clb[0].I[3]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n26' on pin 'I[4]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n26:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[4] -> clb[0].I[4]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n30' on pin 'I[5]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n30:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[5] -> clb[0].I[5]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n35' on pin 'I[6]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n35:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[6] -> clb[0].I[6]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[3]' on pin 'I[7]' during repacking (constrained net name is )
Pb route for Net B[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[7] -> clb[0].I[7]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[0]' on pin 'I[8]' during repacking (constrained net name is )
Pb route for Net B[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[8] -> clb[0].I[8]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[1]' on pin 'I[9]' during repacking (constrained net name is )
Pb route for Net B[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[9] -> clb[0].I[9]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[2]' on pin 'I[10]' during repacking (constrained net name is )
Pb route for Net B[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[10] -> clb[0].I[10]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[1]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n24' on pin 'I[11]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n24:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[11] -> clb[0].I[11]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n22' on pin 'I[12]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n22:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[12] -> clb[0].I[12]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[13]' during repacking (constrained net name is )
Pb route for Net A[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[13] -> clb[0].I[13]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n33' on pin 'I[14]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n33:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[14] -> clb[0].I[14]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n36' on pin 'I[15]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n36:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[15] -> clb[0].I[15]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[1]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[16]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[17]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[18]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[19]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[20]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[21]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[22]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[23]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[24]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[25]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[26]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[27]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[28]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[29]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[30]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[31]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[32]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[33]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[34]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[35]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[36]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[37]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[38]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[39]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'clk[0]' during repacking (constrained net name is )
Pb route for Net Y[0]:
Source node:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[0]
Pb route for Net Y[7]:
Source node:
	clb[0]/fle[4]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[4]
Pb route for Net Y[2]:
Source node:
	clb[0]/fle[5]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[5]
Pb route for Net new_$abc$328$new_n27:
Source node:
	clb[0]/fle[6]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[6]
	clb[0]/fle[7]/ble6[0]/lut6[0].in[1]
Pb route for Net Y[4]:
Source node:
	clb[0]/fle[7]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[7]
Pb route for Net Y[3]:
Source node:
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[18]
Pb route for Net new_$abc$328$new_n25:
Source node:
	clb[0]/fle[9]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[9]
	clb[0]/fle[7]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[1]
Added 23 nets to be routed.
Reroute succeed
Update physical pb 'clb[0][default]/fle[0][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[0]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[0][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[4][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[7]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[4][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[5][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[2]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[5][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[6][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n27'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[6][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[1]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[2]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[3]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[4]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[5]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].out[0]'...
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Update physical pb 'clb[0][default]/fle[7][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[4]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[7][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[1]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[2]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[3]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[4]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[5]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].out[0]'...
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Update physical pb 'clb[0][default]/fle[8][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[3]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[8][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
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Update physical pb 'clb[0][default]/fle[9][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n25'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[9][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[2]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[3]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[4]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[5]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Save net 'A[2]' to physical pb_graph_pin 'clb[0].I[0]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0].I[1]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0].I[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[4]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[4]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0].I[3]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8].in[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0].I[4]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7].in[2]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0].I[5]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4].in[5]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0].I[6]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4].in[2]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0].I[7]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0].I[8]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0].I[9]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0].I[10]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0].I[11]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8].in[4]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0].I[12]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0].I[13]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0].I[14]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4].in[0]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0].I[15]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4].in[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0].out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0].O[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4].out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0].O[4]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5].out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0].O[5]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6].out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0].O[6]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7].in[1]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7].out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0].O[7]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8].out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0].O[18]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9].out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0].O[9]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8].in[1]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[5]'...
Follow the same mapping results for net 'Y[5]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[5]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[5]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[5]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[5]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[5]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[6]'...
Follow the same mapping results for net 'Y[6]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[6]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[6]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[6]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[6]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[6]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[7]'...
Follow the same mapping results for net 'Y[7]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[7]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[7]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[7]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[7]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[7]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[4]'...
Follow the same mapping results for net 'Y[4]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[4]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[4]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[4]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[4]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[4]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[3]'...
Follow the same mapping results for net 'Y[3]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[3]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[3]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[3]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[3]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[3]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[2]'...
Follow the same mapping results for net 'Y[2]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[2]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[2]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[2]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[2]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[2]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[0]'...
Follow the same mapping results for net 'Y[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[0]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[0]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[0]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[0]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[0]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[1]'...
Follow the same mapping results for net 'Y[1]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[1]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[1]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[1]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[1]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[1]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[0]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[0]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[0]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[0]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[0]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[0]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[1]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[1]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[1]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[1]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[1]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[1]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[2]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[2]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[2]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[2]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[2]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[2]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[3]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[3]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[3]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[3]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[3]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[3]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[0]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[0]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[0]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[0]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[0]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[0]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[1]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[1]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[1]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[1]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[1]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[1]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[2]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[2]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[2]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[2]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[2]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[2]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[3]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[3]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[3]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[3]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[3]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[3]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Identify wire LUTs created by repacking
Identified 0 wire LUTs created by repacker
Identify wire LUTs created by repacking took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Build truth tables for physical LUTs
Build truth tables for physical LUTs under clustered block 'new_$abc$328$new_n22'...
Driver atom block: '33'
Pb atom blocks:'33', 
Input nets: new_$abc$328$new_n26  new_$abc$328$new_n23  new_$abc$328$new_n24  new_$abc$328$new_n25  new_$abc$328$new_n27  unconn  
Output net: new_$abc$328$new_n35
Truth table before adaption to fracturable LUT'
	-0-0-- 0
	-01--- 0
	--10-- 0
	0---0- 0
	1---1- 0
Add following truth table to pb_graph_pin 'lut5_out[0]'
	-0-0-1 0
	-01--1 0
	--10-1 0
	0---01 0
	1---11 0

Driver atom block: '24'
Pb atom blocks:'24', '17', 
Input nets: A[1]  B[0]  B[3]  A[0]  B[1]  unconn  
Output net: new_$abc$328$new_n26
Truth table before adaption to fracturable LUT'
	1-1--- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	1-1--1 1

Driver atom block: '17'
Pb atom blocks:'24', '17', 
Input nets: A[1]  B[0]  B[3]  A[0]  B[1]  unconn  
Output net: Y[1]
Truth table before adaption to fracturable LUT'
	0--11- 1
	-0-11- 1
	11-0-- 1
	11--0- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	0--110 1
	-0-110 1
	11-0-0 1
	11--00 1

Driver atom block: '28'
Pb atom blocks:'28', '31', 
Input nets: new_$abc$328$new_n26  new_$abc$328$new_n31  new_$abc$328$new_n32  new_$abc$328$new_n27  unconn  unconn  
Output net: new_$abc$328$new_n30
Truth table before adaption to fracturable LUT'
	-11--- 1
	1-11-- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	-11--1 1
	1-11-1 1

Driver atom block: '31'
Pb atom blocks:'28', '31', 
Input nets: new_$abc$328$new_n26  new_$abc$328$new_n31  new_$abc$328$new_n32  new_$abc$328$new_n27  unconn  unconn  
Output net: new_$abc$328$new_n33
Truth table before adaption to fracturable LUT'
	000--- 1
	-000-- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	000--0 1
	-000-0 1

Driver atom block: '30'
Pb atom blocks:'30', '34', 
Input nets: B[1]  B[3]  A[3]  A[2]  B[2]  unconn  
Output net: new_$abc$328$new_n32
Truth table before adaption to fracturable LUT'
	-101-- 1
	-1-10- 1
	--101- 1
	001-1- 1
	11-1-- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	-101-1 1
	-1-101 1
	--1011 1
	001-11 1
	11-1-1 1

Driver atom block: '34'
Pb atom blocks:'30', '34', 
Input nets: B[1]  B[3]  A[3]  A[2]  B[2]  unconn  
Output net: new_$abc$328$new_n36
Truth table before adaption to fracturable LUT'
	1-111- 0
	-1111- 0
Add following truth table to pb_graph_pin 'lut5_out[1]'
	1-1110 0
	-11110 0

Driver atom block: '32'
Pb atom blocks:'32', 
Input nets: new_$abc$328$new_n30  B[3]  new_$abc$328$new_n33  new_$abc$328$new_n35  A[3]  new_$abc$328$new_n36  
Output net: Y[6]
Truth table before adaption to fracturable LUT'
	1---01 1
	10---1 1
	11--10 1
	0--000 1
	00-0-0 1
	01-011 1
	--0101 1
	-001-1 1
	-10110 1
	0-1-00 1
	001--0 1
	011-11 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	1---01 1
	10---1 1
	11--10 1
	0--000 1
	00-0-0 1
	01-011 1
	--0101 1
	-001-1 1
	-10110 1
	0-1-00 1
	001--0 1
	011-11 1

Driver atom block: '29'
Pb atom blocks:'29', 
Input nets: A[1]  B[0]  B[2]  A[2]  B[1]  A[3]  
Output net: new_$abc$328$new_n31
Truth table before adaption to fracturable LUT'
	1-1110 1
	-10111 1
	111011 1
	111101 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	1-1110 1
	-10111 1
	111011 1
	111101 1

Driver atom block: '22'
Pb atom blocks:'22', 
Input nets: B[1]  A[1]  B[0]  B[2]  A[0]  A[2]  
Output net: new_$abc$328$new_n24
Truth table before adaption to fracturable LUT'
	11-11- 0
	--1111 0
	111--1 0
Add following truth table to pb_graph_pin 'lut6_out[0]'
	11-11- 0
	--1111 0
	111--1 0

Driver atom block: '21'
Pb atom blocks:'21', '26', 
Input nets: new_$abc$328$new_n29  new_$abc$328$new_n30  new_$abc$328$new_n33  B[3]  A[0]  unconn  
Output net: new_$abc$328$new_n23
Truth table before adaption to fracturable LUT'
	---11- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	---111 1

Driver atom block: '26'
Pb atom blocks:'21', '26', 
Input nets: new_$abc$328$new_n29  new_$abc$328$new_n30  new_$abc$328$new_n33  B[3]  A[0]  unconn  
Output net: Y[5]
Truth table before adaption to fracturable LUT'
	01---- 1
	100--- 1
	0-1--- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	01---0 1
	100--0 1
	0-1--0 1

Driver atom block: '27'
Pb atom blocks:'27', 
Input nets: new_$abc$328$new_n27  new_$abc$328$new_n23  new_$abc$328$new_n24  new_$abc$328$new_n26  new_$abc$328$new_n25  new_$abc$328$new_n22  
Output net: new_$abc$328$new_n29
Truth table before adaption to fracturable LUT'
	0-10-- 1
	1-11-- 1
	0--0-0 1
	1--1-0 1
	00-0-- 1
	10-1-- 1
	-01--0 1
	0--00- 1
	1--10- 1
	--1-00 1
	-01-0- 1
	-0--00 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	0-10-- 1
	1-11-- 1
	0--0-0 1
	1--1-0 1
	00-0-- 1
	10-1-- 1
	-01--0 1
	0--00- 1
	1--10- 1
	--1-00 1
	-01-0- 1
	-0--00 1

Driver atom block: '20'
Pb atom blocks:'20', 
Input nets: A[1]  B[2]  B[0]  B[1]  A[2]  A[0]  
Output net: new_$abc$328$new_n22
Truth table before adaption to fracturable LUT'
	101101 1
	111111 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	101101 1
	111111 1

Build truth tables for physical LUTs under clustered block 'new_$abc$328$new_n25'...
Driver atom block: '16'
Pb atom blocks:'16', 
Input nets: A[0]  unconn  unconn  unconn  B[0]  unconn  
Output net: Y[0]
Truth table before adaption to fracturable LUT'
	1---1- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	1---11 1

Driver atom block: '36'
Pb atom blocks:'36', 
Input nets: new_$abc$328$new_n33  new_$abc$328$new_n36  new_$abc$328$new_n35  B[3]  A[3]  new_$abc$328$new_n30  
Output net: Y[7]
Truth table before adaption to fracturable LUT'
	-0-11- 1
	0-111- 1
	001--- 1
	---111 1
	-0---1 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	-0-11- 1
	0-111- 1
	001--- 1
	---111 1
	-0---1 1

Driver atom block: '18'
Pb atom blocks:'18', 
Input nets: A[0]  B[0]  A[1]  A[2]  B[1]  B[2]  
Output net: Y[2]
Truth table before adaption to fracturable LUT'
	00--0- 0
	000--- 0
	-0--00 0
	-00--0 0
	101-11 0
	0--00- 0
	0-00-- 0
	11-0-0 0
	01111- 0
	11-1-1 0
Add following truth table to pb_graph_pin 'lut6_out[0]'
	00--0- 0
	000--- 0
	-0--00 0
	-00--0 0
	101-11 0
	0--00- 0
	0-00-- 0
	11-0-0 0
	01111- 0
	11-1-1 0

Driver atom block: '25'
Pb atom blocks:'25', 
Input nets: A[1]  A[2]  B[1]  B[0]  B[2]  A[3]  
Output net: new_$abc$328$new_n27
Truth table before adaption to fracturable LUT'
	--0-0- 0
	-0---0 0
	----00 0
	000--- 0
	1-1--0 0
	-000-- 0
	011011 0
	-1-10- 0
	10111- 0
	1101-1 0
Add following truth table to pb_graph_pin 'lut6_out[0]'
	--0-0- 0
	-0---0 0
	----00 0
	000--- 0
	1-1--0 0
	-000-- 0
	011011 0
	-1-10- 0
	10111- 0
	1101-1 0

Driver atom block: '19'
Pb atom blocks:'19', 
Input nets: new_$abc$328$new_n25  new_$abc$328$new_n27  new_$abc$328$new_n26  new_$abc$328$new_n22  new_$abc$328$new_n23  new_$abc$328$new_n24  
Output net: Y[4]
Truth table before adaption to fracturable LUT'
	00100- 1
	01000- 1
	00011- 1
	01111- 1
	10010- 1
	11110- 1
	10001- 1
	11101- 1
	-00100 1
	-11100 1
	-00010 1
	-11010 1
	1000-0 1
	1110-0 1
	101110 1
	110110 1
	-01001 1
	-10001 1
	-00111 1
	-11111 1
	0010-1 1
	0100-1 1
	001-01 1
	010-01 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	00100- 1
	01000- 1
	00011- 1
	01111- 1
	10010- 1
	11110- 1
	10001- 1
	11101- 1
	-00100 1
	-11100 1
	-00010 1
	-11010 1
	1000-0 1
	1110-0 1
	101110 1
	110110 1
	-01001 1
	-10001 1
	-00111 1
	-11111 1
	0010-1 1
	0100-1 1
	001-01 1
	010-01 1

Driver atom block: '35'
Pb atom blocks:'35', 
Input nets: new_$abc$328$new_n23  new_$abc$328$new_n25  unconn  new_$abc$328$new_n22  new_$abc$328$new_n24  unconn  
Output net: Y[3]
Truth table before adaption to fracturable LUT'
	00-00- 1
	10-10- 1
	00-11- 1
	10-01- 1
	01-10- 1
	11-00- 1
	01-01- 1
	11-11- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	00-000 1
	10-100 1
	00-110 1
	10-010 1
	01-100 1
	11-000 1
	01-010 1
	11-110 1

Driver atom block: '23'
Pb atom blocks:'23', 
Input nets: B[1]  B[2]  B[0]  A[2]  A[1]  A[3]  
Output net: new_$abc$328$new_n25
Truth table before adaption to fracturable LUT'
	01--10 1
	-1-010 1
	1--100 1
	10-1-0 1
	010-1- 1
	-1001- 1
	1-010- 1
	1001-- 1
	0-1-01 1
	001--1 1
	--1001 1
	-010-1 1
	111111 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	01--10 1
	-1-010 1
	1--100 1
	10-1-0 1
	010-1- 1
	-1001- 1
	1-010- 1
	1001-- 1
	0-1-01 1
	001--1 1
	--1001 1
	-010-1 1
	111111 1

Build truth tables for physical LUTs under clustered block 'out:Y[5]'...
Build truth tables for physical LUTs under clustered block 'out:Y[6]'...
Build truth tables for physical LUTs under clustered block 'out:Y[7]'...
Build truth tables for physical LUTs under clustered block 'out:Y[4]'...
Build truth tables for physical LUTs under clustered block 'out:Y[3]'...
Build truth tables for physical LUTs under clustered block 'out:Y[2]'...
Build truth tables for physical LUTs under clustered block 'out:Y[0]'...
Build truth tables for physical LUTs under clustered block 'out:Y[1]'...
Build truth tables for physical LUTs under clustered block 'A[0]'...
Build truth tables for physical LUTs under clustered block 'A[1]'...
Build truth tables for physical LUTs under clustered block 'A[2]'...
Build truth tables for physical LUTs under clustered block 'A[3]'...
Build truth tables for physical LUTs under clustered block 'B[0]'...
Build truth tables for physical LUTs under clustered block 'B[1]'...
Build truth tables for physical LUTs under clustered block 'B[2]'...
Build truth tables for physical LUTs under clustered block 'B[3]'...
Build truth tables for physical LUTs took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml

Confirm selected options when call command 'build_architecture_bitstream':
--write_file: fabric_indepenent_bitstream.xml
--read_file: off
--no_time_stamp: off
--verbose: off

Build fabric-independent bitstream for implementation 'mult4'

Generating bitstream for Switch blocks...Done
Generating bitstream for X-direction Connection blocks ...Done
Generating bitstream for Y-direction Connection blocks ...Done

Build fabric-independent bitstream for implementation 'mult4'
 took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Overwrite Bitstream


Overwrite Bitstream
 took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Warning 36: Directory path is empty and nothing will be created.
Write 8416 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
Write 8416 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.01 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Build non-fabric bitstream for implementation 'mult4'


Build non-fabric bitstream for implementation 'mult4'
 took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: build_fabric_bitstream

Confirm selected options when call command 'build_fabric_bitstream':
--verbose: off

Build fabric dependent bitstream


Build fabric dependent bitstream
 took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit --no_time_stamp

Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.bit
--format: plain_text
--filter_value: off
--path_only: off
--value_only: off
--trim_path: off
--fast_configuration: off
--keep_dont_care_bits: off
--wl_decremental_order: off
--no_time_stamp: on
--verbose: off
Warning 37: Directory path is empty and nothing will be created.
Write 8416 fabric bitstream into plain text file 'fabric_bitstream.bit'
Write 8416 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml --no_time_stamp

Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.xml
--format: xml
--filter_value: off
--path_only: off
--value_only: off
--trim_path: off
--fast_configuration: off
--keep_dont_care_bits: off
--wl_decremental_order: off
--no_time_stamp: on
--verbose: off
Warning 38: Directory path is empty and nothing will be created.
Write 8416 fabric bitstream into xml file 'fabric_bitstream.xml'
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Write 8416 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_hierarchy --file ./fabric_hierarchy.txt

Confirm selected options when call command 'write_fabric_hierarchy':
--file, -f: ./fabric_hierarchy.txt
--module: off
--filter: off
--depth: off
--exclude_empty_modules: off
--verbose: off
Write fabric hierarchy to plain-text file './fabric_hierarchy.txt'
Outputted 1 modules as root
Write fabric hierarchy to plain-text file './fabric_hierarchy.txt' took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_io_info --file ./fabric_io_location.xml --verbose

Confirm selected options when call command 'write_fabric_io_info':
--file, -f: ./fabric_io_location.xml
--no_time_stamp: off
--verbose: on
Warning 39: Directory '.' already exists. Will overwrite contents
Write fabric I/O information to an XML file './fabric_io_location.xml'
Outputted 64 I/Os to XML file: ./fabric_io_location.xml
Write fabric I/O information to an XML file './fabric_io_location.xml' took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_verilog --file /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose  --default_net_type wire

Confirm selected options when call command 'write_fabric_verilog':
--file, -f: /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC
--constant_undriven_inputs: off
--explicit_port_mapping: on
--include_timing: on
--print_user_defined_template: on
--default_net_type: wire
--no_time_stamp: off
--use_relative_path: off
--little_endian, -le: off
--verbose: on
Write Verilog netlists for FPGA fabric

Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC'
Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module'
Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb'
Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/routing'
Generating Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/inv_buf_passgate.v' for essential gates...Done
Writing Verilog netlist for configuration decoders '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/arch_encoder.v'...Done
Writing Verilog netlist for local decoders for multiplexers '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/local_encoder.v'...Done
Writing Verilog netlist for Multiplexer primitives '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/mux_primitives.v' ...Done
Writing Verilog netlist for Multiplexers '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/muxes.v' ...Done
Writing Verilog netlist for LUTs '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.v'...Done
Writing Verilog netlist for wires '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/wires.v'...Done
Writing Verilog netlist for memories '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/memories.v' ...Done
Writing Verilog netlist for shift register banks '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/shift_register_banks.v' ...Done
Creating template for user-defined Verilog modules '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_templates.v'...Done

Writing logical tiles...
Writing Verilog netlists for logic tile 'io' ...
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_io_mode_physical__iopad.v' for primitive pb_type 'iopad' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_io_mode_physical__iopad'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_io_mode_io_.v' for pb_type 'io' ...
Writing Verilog codes of pb_type 'logical_tile_io_mode_io_'...Done
Done

Writing Verilog netlists for logic tile 'clb' ...
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut6.v' for primitive pb_type 'frac_lut6' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut6'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v' for pb_type 'frac_logic' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v' for primitive pb_type 'ff' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v' for pb_type 'fabric' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle.v' for pb_type 'fle' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_clb_.v' for pb_type 'clb' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_clb_'...Done
Done

Writing logical tiles...Done

Building physical tiles...
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_top.v' for physical tile 'io' at top side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_right.v' for physical tile 'io' at right side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_bottom.v' for physical tile 'io' at bottom side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_left.v' for physical tile 'io' at left side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_clb.v' for physical_tile 'clb'...Done
Building physical tiles...Done

Writing Verilog netlist for top-level module of FPGA fabric '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/fpga_top.v'...Done
Written 74 Verilog modules in total
Write Verilog netlists for FPGA fabric
 took 0.02 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: write_full_testbench --file ./SRC --reference_benchmark_file_path mult4_output_verilog.v --explicit_port_mapping --bitstream fabric_bitstream.bit --simulator iverilog --default_net_type wire

Confirm selected options when call command 'write_full_testbench':
--file, -f: ./SRC
--dut_module: off
--bitstream: fabric_bitstream.bit
--simulator: iverilog
--fabric_netlist_file_path: off
--pin_constraints_file, -pcf: off
--bus_group_file, -bgf: off
--reference_benchmark_file_path: mult4_output_verilog.v
--fast_configuration: off
--explicit_port_mapping: on
--default_net_type: wire
--no_self_checking: off
--include_signal_init: off
--no_time_stamp: off
--use_relative_path: off
--little_endian, -le: off
--verbose: off
Write Verilog full testbenches for FPGA fabric

# Write autocheck testbench for FPGA top-level Verilog netlist for 'mult4'
Will use 8417 configuration clock cycles to top testbench
# Write autocheck testbench for FPGA top-level Verilog netlist for 'mult4' took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Write Verilog full testbenches for FPGA fabric
 took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: write_pnr_sdc --file ./SDC

Confirm selected options when call command 'write_pnr_sdc':
--file, -f: ./SDC
--flatten_names: off
--hierarchical: off
--output_hierarchy: off
--time_unit: off
--constrain_global_port: off
--constrain_non_clock_global_port: off
--constrain_grid: off
--constrain_sb: off
--constrain_cb: off
--constrain_configurable_memory_outputs: off
--constrain_routing_multiplexer_outputs: off
--constrain_switch_block_outputs: off
--constrain_zero_delay_paths: off
--no_time_stamp: off
--verbose: off
Succeed to create directory './SDC'
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc'
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc'
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc'
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.01 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc'
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Write SDC for constrain Switch Block timing for P&R flow
Write SDC for constrain Switch Block timing for P&R flow took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Write SDC for constrain Connection Block timing for P&R flow
Write SDC for constrain Connection Block timing for P&R flow took 0.00 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)
Write SDC for constraining grid timing for P&R flow
Write SDC for constraining grid timing for P&R flow took 0.01 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc

Confirm selected options when call command 'write_sdc_disable_timing_configure_ports':
--file, -f: ./SDC/disable_configure_ports.sdc
--flatten_names: off
--no_time_stamp: off
--verbose: off
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc'
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.01 seconds (max_rss 64.6 MiB, delta_rss +0.0 MiB)

Command line to execute: exit

Confirm selected options when call command 'exit':

Finish execution with 0 errors

The entire OpenFPGA flow took 0.157156 seconds

Thank you for using OpenFPGA!
Incr Slack updates 35 in 3.6289e-05 sec
Full Max Req/Worst Slack updates 7 in 4.452e-06 sec
Incr Max Req/Worst Slack updates 28 in 1.364e-05 sec
Incr Criticality updates 19 in 3.6864e-05 sec
Full Criticality updates 16 in 2.9008e-05 sec
0

[shimoshida]

• Can you try to add --constant_method_method route to vpr in your openfpga shell script ? See details here
• Can you share the openfpgashell.log under ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH?

I also tried adding the --constant_net_method route option to the above flow(mult4.v + yosys_vpr), but the result did not change.

Simulation start
Mismatch on Y_1__fpga at time =           84187.61ns
Mismatch on Y_2__fpga at time =           84187.61ns
Mismatch on Y_3__fpga at time =           84187.61ns
Mismatch on Y_4__fpga at time =           84187.61ns
Mismatch on Y_5__fpga at time =           84187.61ns
Mismatch on Y_6__fpga at time =           84187.61ns
Mismatch on Y_7__fpga at time =           84187.61ns
Mismatch on Y_2__fpga at time =           84194.65ns
Mismatch on Y_7__fpga at time =           84194.65ns
Mismatch on Y_0__fpga at time =           84198.18ns
Mismatch on Y_1__fpga at time =           84198.18ns
Mismatch on Y_2__fpga at time =           84201.70ns
Mismatch on Y_1__fpga at time =           84208.74ns
Mismatch on Y_2__fpga at time =           84208.74ns
Mismatch on Y_7__fpga at time =           84212.26ns
Mismatch on Y_2__fpga at time =           84215.79ns
Mismatch on Y_0__fpga at time =           84222.83ns
Mismatch on Y_1__fpga at time =           84222.83ns
Mismatch on Y_2__fpga at time =           84222.83ns
Mismatch on Y_7__fpga at time =           84222.83ns
Mismatch on Y_0__fpga at time =           84229.87ns
Mismatch on Y_7__fpga at time =           84229.87ns
Mismatch on Y_2__fpga at time =           84236.92ns
Simulation Failed with          23 error(s)

openfpgashell.log in this case is as follows.

openfpgashell.log

/home/moshida/OpenFPGA/build/openfpga/openfpga -batch -f mult4_run.openfpga
Reading script file mult4_run.openfpga...

            ___                   _____ ____   ____    _     
           / _ \ _ __   ___ _ __ |  ___|  _ \ / ___|  / \    
          | | | | '_ \ / _ \ '_ \| |_  | |_) | |  _  / _ \   
          | |_| | |_) |  __/ | | |  _| |  __/| |_| |/ ___ \  
           \___/| .__/ \___|_| |_|_|   |_|    \____/_/   \_\ 
                |_|                                          

               OpenFPGA: An Open-source FPGA IP Generator
                     Versatile Place and Route (VPR)
                           FPGA-Verilog
                           FPGA-SPICE
                           FPGA-SDC
                           FPGA-Bitstream

             This is a free software under the MIT License

             Copyright (c) 2018 LNIS - The University of Utah

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.



Command line to execute: vpr /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run067/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_tileable_40nm.xml mult4.blif --clock_modeling route --device 2x2 --route_chan_width 20 --skip_sync_clustering_and_routing_results on --constant_net_method route
VPR FPGA Placement and Routing.
Version: 9.0.0-dev+v8.0.0-14872-gd3c57bc97
Revision: v8.0.0-14872-gd3c57bc97
Compiled: 2026-01-15T16:57:17
Compiler: GNU 11.4.0 on Linux-6.8.0-87-generic x86_64
Build Info: release IPO VTR_ASSERT_LEVEL=2

University of Toronto
verilogtorouting.org
vtr-users@googlegroups.com
This is free open source code under MIT license.

VPR was run with the following command-line:
vpr /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run067/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_tileable_40nm.xml mult4.blif --clock_modeling route --device 2x2 --route_chan_width 20 --skip_sync_clustering_and_routing_results on --constant_net_method route

Using up to 1 parallel worker(s)

Architecture file: /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run067/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_tileable_40nm.xml
Circuit name: mult4

# Loading Architecture Description
Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 3: Model 'frac_lut6' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 4: Model 'frac_lut6' output port 'lut6_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 5: Model 'frac_lut6' output port 'lut5_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
mode 'io[physical]' is defined by user to be disabled in packing
mode 'fle[physical]' is defined by user to be disabled in packing
mode 'fabric[default]' is defined by user to be disabled in packing
mode 'frac_logic[default]' is defined by user to be disabled in packing
# Loading Architecture Description took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)

Timing analysis: ON
Circuit netlist file: mult4.net
Circuit placement file: mult4.place
Circuit routing file: mult4.route
Circuit SDC file: mult4.sdc
Vpr floorplanning constraints file: not specified

Packer: ENABLED
Placer: ENABLED
Analytical Placer: DISABLED
Router: ENABLED
Analysis: SKIP IF PRIOR FAIL

VPR was run with the following options:

NetlistOpts.absorb_buffer_luts            : true
NetlistOpts.sweep_dangling_primary_ios    : true
NetlistOpts.sweep_dangling_nets           : true
NetlistOpts.sweep_dangling_blocks         : true
NetlistOpts.sweep_constant_primary_outputs: false
NetlistOpts.netlist_verbosity             : 1
NetlistOpts.const_gen_inference           : COMB_SEQ

PackerOpts.allow_unrelated_clustering: auto
PackerOpts.timing_gain_weight: 0.750000
PackerOpts.connection_gain_weight: 0.900000
PackerOpts.cluster_seed_type: BLEND2
PackerOpts.connection_driven: true
PackerOpts.timing_driven: true
PackerOpts.target_external_pin_util: auto

PlacerOpts.place_freq: PLACE_ONCE
PlacerOpts.place_algorithm: CRITICALITY_TIMING_PLACE
PlacerOpts.pad_loc_type: FREE
PlacerOpts.constraints_file: No constraints file given
PlacerOpts.place_chan_width: 20
PlacerOpts.inner_loop_recompute_divider: 0
PlacerOpts.recompute_crit_iter: 1
PlacerOpts.timing_tradeoff: 0.500000
PlacerOpts.td_place_exp_first: 1.000000
PlacerOpts.td_place_exp_last: 8.000000
PlacerOpts.delay_offset: 0.000000
PlacerOpts.delay_ramp_delta_threshold: -1
PlacerOpts.delay_ramp_slope: 0.000000
PlacerOpts.tsu_rel_margin: 1.000000
PlacerOpts.tsu_abs_margin: 0.000000
PlacerOpts.post_place_timing_report_file: 
PlacerOpts.allowed_tiles_for_delay_model: 
PlacerOpts.delay_model_reducer: MIN
PlacerOpts.delay_model_type: SIMPLE
PlacerOpts.rlim_escape_fraction: 0.000000
PlacerOpts.move_stats_file: 
PlacerOpts.placement_saves_per_temperature: 0
PlacerOpts.effort_scaling: CIRCUIT
PlacerOpts.place_delta_delay_matrix_calculation_method: ASTAR_ROUTE
PlaceOpts.seed: 1
AnnealSched.type: AUTO_SCHED
AnnealSched.inner_num: 0.500000

RouterOpts.route_type: DETAILED
RouterOpts.flat_routing: false
RouterOpts.choke_points: on
RouterOpts.router_algorithm: TIMING_DRIVEN
RouterOpts.base_cost_type: DELAY_NORMALIZED_LENGTH
RouterOpts.fixed_channel_width: 20
RouterOpts.check_route: FULL
RouterOpts.acc_fac: 1.000000
RouterOpts.bb_factor: 3
RouterOpts.bend_cost: 0.000000
RouterOpts.first_iter_pres_fac: 0.000000
RouterOpts.initial_pres_fac: 0.500000
RouterOpts.pres_fac_mult: 1.300000
RouterOpts.max_pres_fac: 1000.000000
RouterOpts.max_router_iterations: 50
RouterOpts.min_incremental_reroute_fanout: 16
RouterOpts.initial_acc_cost_chan_congestion_threshold: 0.500000
RouterOpts.initial_acc_cost_chan_congestion_weight: 0.500000
RouterOpts.do_check_rr_graph: true
RouterOpts.verify_binary_search: false
RouterOpts.min_channel_width_hint: 0
RouterOpts.read_rr_edge_metadata: false
RouterOpts.exit_after_first_routing_iteration: false
RouterOpts.astar_fac: 1.200000
RouterOpts.astar_offset: 0.000000
RouterOpts.router_profiler_astar_fac: 1.200000
RouterOpts.enable_parallel_connection_router: false
RouterOpts.post_target_prune_fac: 1.200000
RouterOpts.post_target_prune_offset: 0
RouterOpts.multi_queue_num_threads: 1
RouterOpts.multi_queue_num_queues: 2
RouterOpts.multi_queue_direct_draining: false
RouterOpts.criticality_exp: 1.000000
RouterOpts.max_criticality: 0.990000
RouterOpts.init_wirelength_abort_threshold: 0.850000
RouterOpts.incr_reroute_delay_ripup: AUTO
RouterOpts.save_routing_per_iteration: false
RouterOpts.congested_routing_iteration_threshold_frac: 1.000000
RouterOpts.high_fanout_threshold: 64
RouterOpts.router_debug_net: -2
RouterOpts.router_debug_sink_rr: -2
RouterOpts.router_debug_iteration: -2
RouterOpts.max_convergence_count: 1
RouterOpts.reconvergence_cpd_threshold: 0.990000
RouterOpts.update_lower_bound_delays: true
RouterOpts.first_iteration_timing_report_file: 
RouterOpts.route_bb_update: DYNAMIC
RouterOpts.lookahead_type: MAP
RouterOpts.initial_timing: LOOKAHEAD
RouterOpts.router_heap: FOUR_ARY_HEAP
RouterOpts.routing_failure_predictor = SAFE
RouterOpts.routing_budgets_algorithm = DISABLE

AnalysisOpts.gen_post_synthesis_netlist: false
AnalysisOpts.gen_post_implementation_merged_netlist: false
AnalysisOpts.gen_post_implementation_sdc: false
AnalysisOpts.timing_report_npaths: 100
AnalysisOpts.timing_report_skew: false
AnalysisOpts.echo_dot_timing_graph_node: -1
AnalysisOpts.timing_report_detail: NETLIST
AnalysisOpts.post_synth_netlist_unconn_input_handling: UNCONNECTED
AnalysisOpts.post_synth_netlist_unconn_output_handling: UNCONNECTED
AnalysisOpts.post_synth_netlist_module_parameters: on

# Building complex block graph
# Building complex block graph took 0.01 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
Circuit file: mult4.blif
# Load circuit
# Load circuit took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
# Clean circuit
Absorbed 0 LUT buffers
Inferred    0 additional primitive pins as constant generators since they have no combinationally connected inputs
Inferred    0 additional primitive pins as constant generators due to constant inputs
Swept input(s)      : 0
Swept output(s)     : 0 (0 dangling, 0 constant)
Swept net(s)        : 0
Swept block(s)      : 0
Constant Pins Marked: 0
# Clean circuit took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
# Compress circuit
# Compress circuit took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
# Verify circuit
# Verify circuit took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
Circuit Statistics:
  Blocks: 37
    .input :       8
    .names :      21
        2-LUT:       3
        3-LUT:       1
        4-LUT:       4
        5-LUT:       3
        6-LUT:      10
    .output:       8
  Nets  : 29
    Avg Fanout:     3.7
    Max Fanout:     9.0
    Min Fanout:     1.0
  Netlist Clocks: 0
# Build Timing Graph
  Timing Graph Nodes: 137
  Timing Graph Edges: 208
  Timing Graph Levels: 8
# Build Timing Graph took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
Netlist contains 0 clocks
# Load Timing Constraints

SDC file 'mult4.sdc' not found
Setting default timing constraints:
   * constrain all primary inputs and primary outputs on a virtual external clock 'virtual_io_clock'
   * optimize virtual clock to run as fast as possible
Timing constraints created 1 clocks
  Constrained Clock 'virtual_io_clock' (Virtual Clock)

# Load Timing Constraints took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
# Packing
## Prepacker
## Prepacker took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
## Initializing Pre-Cluster Timing
Using inter-cluster delay: 1.33777e-09
## Initializing Pre-Cluster Timing took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
Begin packing 'mult4.blif'.

After removing unused inputs...
	total blocks: 37, total nets: 29, total inputs: 8, total outputs: 8
Packing with pin utilization targets: io:1,1 clb:0.8,0.6
Packing with high fanout thresholds: io:128 clb:32
Starting Clustering - Clustering Progress: 
-------------------   --------------------------   ---------
Molecules processed   Number of clusters created   FPGA size
-------------------   --------------------------   ---------
    14/37       37%                            1     4 x 4     
    21/37       56%                            2     4 x 4     
    22/37       59%                            3     4 x 4     
    23/37       62%                            4     4 x 4     
    24/37       64%                            5     4 x 4     
    25/37       67%                            6     4 x 4     
    26/37       70%                            7     4 x 4     
    27/37       72%                            8     4 x 4     
    28/37       75%                            9     4 x 4     
    29/37       78%                           10     4 x 4     
    30/37       81%                           11     4 x 4     
    31/37       83%                           12     4 x 4     
    32/37       86%                           13     4 x 4     
    33/37       89%                           14     4 x 4     
    34/37       91%                           15     4 x 4     
    35/37       94%                           16     4 x 4     
    36/37       97%                           17     4 x 4     
    37/37      100%                           18     4 x 4     

Logic Element (fle) detailed count:
  Total number of Logic Elements used : 17
  LEs used for logic and registers    : 0
  LEs used for logic only             : 17
  LEs used for registers only         : 0

FPGA sized to 4 x 4 (2x2)
Device Utilization: 0.25 (target 1.00)
	Block Utilization: 0.25 Type: io
	Block Utilization: 0.50 Type: clb

Final Clustering Statistics: 
----------   --------   ------------------------------------   --------------------------
Block Type   # Blocks   Avg. # of input clocks and pins used   Avg. # of output pins used
----------   --------   ------------------------------------   --------------------------
     EMPTY          0                                      0                            0   
        io         16                                    0.5                          0.5   
       clb          2                                     13                            9   
Absorbed logical nets 3 out of 29 nets, 26 nets not absorbed.

Netlist conversion complete.

Incr Slack updates 1 in 1.216e-06 sec
Full Max Req/Worst Slack updates 1 in 1.956e-06 sec
Incr Max Req/Worst Slack updates 0 in 0 sec
Incr Criticality updates 0 in 0 sec
Full Criticality updates 1 in 2.304e-06 sec
# Packing took 0.01 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
# Load packing
## Loading packed FPGA netlist file.
Netlist generated from file 'mult4.net'.
Detected 0 constant generators (to see names run with higher pack verbosity)
## Loading packed FPGA netlist file. took 0.00 seconds (max_rss 30.0 MiB, delta_rss +0.0 MiB)
Completed clustering consistency check successfully.
Cluster level netlist and block usage statistics
Netlist num_nets: 26
Netlist num_blocks: 18
Netlist EMPTY blocks: 0.
Netlist io blocks: 16.
Netlist clb blocks: 2.
Netlist inputs pins: 8
Netlist output pins: 8

Pb types usage...
  io             : 16
   inpad         : 8
   outpad        : 8
  clb            : 2
   fle           : 17
    lut5inter    : 7
     ble5        : 11
      lut5       : 11
       lut       : 11
    ble6         : 10
     lut6        : 10
      lut        : 10

# Load packing took 0.03 seconds (max_rss 64.3 MiB, delta_rss +34.3 MiB)
# Create Device
## Build Device Grid
FPGA sized to 4 x 4: 16 grid tiles (2x2)
## Build Device Grid took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph
X-direction routing channel width is 20
Y-direction routing channel width is 20
### Build RR Graph Edges
### Build RR Graph Edges took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
  RR Graph Nodes: 744
  RR Graph Edges: 1732
# Create Device took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Resource usage...
	Netlist
		16	blocks of type: io
	Architecture
		64	blocks of type: io
	Netlist
		2	blocks of type: clb
	Architecture
		4	blocks of type: clb

Device Utilization: 0.25 (target 1.00)
	Physical Tile io:
	Block Utilization: 0.25 Logical Block: io
	Physical Tile clb:
	Block Utilization: 0.50 Logical Block: clb


# Computing router lookahead map
## Computing wire lookahead
## Computing wire lookahead took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
## Computing src/opin lookahead
## Computing src/opin lookahead took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Computing router lookahead map took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Compressed grid construction
# Compressed grid construction took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Bounding box mode is Cube

# Computing placement delta delay look-up
RR graph channel widths unchanged, skipping RR graph rebuild
Serial Connection Router is being destroyed. Time spent on path search: 0.000 seconds.
# Computing placement delta delay look-up took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Placement
## Initial Placement
Initial placement iteration 0 has finished successfully
## Initial Placement took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Using simple RL 'Softmax agent' for choosing move and block types

Completed placement consistency check successfully.
Initial placement cost: 1 bb_cost: 5.30935 td_cost: 6.47339e-09
Initial placement BB estimate of wirelength: 98
Initial placement estimated Critical Path Delay (CPD): 2.07439 ns
Initial placement estimated setup Total Negative Slack (sTNS): -11.6502 ns
Initial placement estimated setup Worst Negative Slack (sWNS): -2.07439 ns

Initial placement estimated setup slack histogram:
[ -2.1e-09:   -2e-09) 1 ( 12.5%) |****************
[   -2e-09: -1.8e-09) 0 (  0.0%) |
[ -1.8e-09: -1.7e-09) 2 ( 25.0%) |*********************************
[ -1.7e-09: -1.6e-09) 0 (  0.0%) |
[ -1.6e-09: -1.5e-09) 2 ( 25.0%) |*********************************
[ -1.5e-09: -1.4e-09) 0 (  0.0%) |
[ -1.4e-09: -1.2e-09) 0 (  0.0%) |
[ -1.2e-09: -1.1e-09) 0 (  0.0%) |
[ -1.1e-09:   -1e-09) 0 (  0.0%) |
[   -1e-09: -8.9e-10) 3 ( 37.5%) |*************************************************
Placement contains 0 placement macros involving 0 blocks (average macro size -nan)

Moves per temperature: 23

---- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
Tnum   Time       T Av Cost Av BB Cost Av TD Cost     CPD       sTNS     sWNS Ac Rate Std Dev  R lim Crit Exp Tot Moves  Alpha
      (sec)                                          (ns)       (ns)     (ns)                                                 
---- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
   1    0.0 6.1e-03   0.999       5.14 6.4215e-09   2.074      -11.7   -2.074   0.696  0.0061    3.0     1.00        23  1.000
   2    0.0 5.8e-03   0.997       5.05 6.3206e-09   2.074      -11.3   -2.074   0.696  0.0051    3.0     1.00        46  0.950
   3    0.0 5.5e-03   1.012       5.15 6.34e-09     2.074      -11.3   -2.074   0.478  0.0081    3.0     1.00        69  0.950
   4    0.0 5.3e-03   0.981       5.10 6.3132e-09   2.098      -11.6   -2.098   0.522  0.0035    3.0     1.00        92  0.950
   5    0.0 5.0e-03   0.992       4.93 6.3449e-09   2.074      -11.3   -2.074   0.261  0.0045    3.0     1.00       115  0.950
   6    0.0 4.7e-03   0.984       4.80 4.9649e-09   2.074      -11.3   -2.074   0.304  0.0038    2.5     2.88       138  0.950
   7    0.0 4.5e-03   1.014       4.85 4.5973e-09   2.074      -11.6   -2.074   0.565  0.0105    2.1     4.05       161  0.950
   8    0.0 4.3e-03   1.005       5.01 5.0687e-09   2.098      -11.7   -2.098   0.391  0.0077    2.4     3.12       184  0.950
   9    0.0 4.1e-03   0.989       5.00 4.5274e-09   2.169      -11.8   -2.169   0.522  0.0109    2.3     3.53       207  0.950
  10    0.0 3.9e-03   0.979       4.79 4.6982e-09   2.169      -11.8   -2.169   0.391  0.0090    2.5     2.87       230  0.950
  11    0.0 3.7e-03   1.011       4.88 4.7736e-09   2.074      -11.3   -2.074   0.348  0.0068    2.3     3.29       253  0.950
  12    0.0 3.5e-03   0.996       4.92 4.4879e-09   2.074      -11.3   -2.074   0.435  0.0055    2.1     4.05       276  0.950
  13    0.0 3.3e-03   0.999       4.82 4.4713e-09   2.074      -11.3   -2.074   0.348  0.0002    2.1     4.09       299  0.950
  14    0.0 3.1e-03   0.997       4.80 4.2635e-09   2.074      -11.3   -2.074   0.348  0.0031    1.9     4.77       322  0.950
  15    0.0 3.0e-03   1.006       4.90 4.1033e-09   2.074      -11.3   -2.074   0.522  0.0041    1.7     5.39       345  0.950
  16    0.0 2.8e-03   0.997       4.90 4.2303e-09   2.074      -11.3   -2.074   0.261  0.0014    1.9     4.89       368  0.950
  17    0.0 2.7e-03   0.999       4.91 3.9513e-09   2.074      -11.3   -2.074   0.478  0.0027    1.5     6.08       391  0.950
  18    0.0 2.6e-03   0.992       4.81 3.995e-09    2.074      -11.3   -2.074   0.478  0.0050    1.6     5.87       414  0.950
  19    0.0 2.4e-03   1.002       4.78 4.0425e-09   2.074      -11.3   -2.074   0.261  0.0031    1.7     5.65       437  0.950
  20    0.0 2.3e-03   1.002       4.86 3.8312e-09   2.074      -11.3   -2.074   0.391  0.0034    1.4     6.70       460  0.950
  21    0.0 2.2e-03   0.997       4.85 3.7898e-09   2.074      -11.3   -2.074   0.348  0.0045    1.3     6.93       483  0.950
  22    0.0 2.1e-03   0.990       4.74 3.7203e-09   2.074      -11.3   -2.074   0.304  0.0044    1.2     7.36       506  0.950
  23    0.0 2.0e-03   0.999       4.69 3.6359e-09   2.074      -11.3   -2.074   0.174  0.0014    1.0     7.92       529  0.950
  24    0.0 1.9e-03   1.004       4.70 3.6242e-09   2.074      -11.3   -2.074   0.391  0.0024    1.0     8.00       552  0.950
  25    0.0 1.8e-03   1.000       4.72 3.6242e-09   2.074      -11.3   -2.074   0.304  0.0000    1.0     8.00       575  0.950
  26    0.0 1.7e-03   1.000       4.72 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0000    1.0     8.00       598  0.950
  27    0.0 1.6e-03   0.998       4.70 3.6242e-09   2.074      -11.3   -2.074   0.435  0.0011    1.0     8.00       621  0.950
  28    0.0 1.5e-03   1.005       4.77 3.6242e-09   2.074      -11.3   -2.074   0.130  0.0029    1.0     8.00       644  0.950
Agent's 2nd state: 
  29    0.0 1.2e-03   0.998       4.74 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0038    1.0     8.00       667  0.800
Checkpoint saved: bb_costs=4.68206, TD costs=3.62421e-09, CPD=  2.074 (ns) 
  30    0.0 1.2e-03   1.000       4.68 3.6242e-09   2.074      -11.3   -2.074   0.304  0.0011    1.0     8.00       690  0.950
  31    0.0 1.1e-03   1.000       4.66 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0000    1.0     8.00       713  0.950
  32    0.0 1.1e-03   1.000       4.66 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       736  0.950
  33    0.0 8.4e-04   1.000       4.66 3.6242e-09   2.074      -11.3   -2.074   0.043  0.0000    1.0     8.00       759  0.800
  34    0.0 6.7e-04   0.998       4.64 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0014    1.0     8.00       782  0.800
  35    0.0 6.4e-04   1.000       4.65 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       805  0.950
  36    0.0 5.1e-04   1.000       4.65 3.6242e-09   2.074      -11.3   -2.074   0.217  0.0011    1.0     8.00       828  0.800
  37    0.0 4.9e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0003    1.0     8.00       851  0.950
  38    0.0 4.6e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       874  0.950
  39    0.0 3.7e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.174  0.0000    1.0     8.00       897  0.800
  40    0.0 3.5e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.087  0.0000    1.0     8.00       920  0.950
  41    0.0 2.8e-04   1.000       4.62 3.6242e-09   2.074      -11.3   -2.074   0.130  0.0000    1.0     8.00       943  0.800
  42    0.0 2.2e-04   0.997       4.60 3.6242e-09   2.074      -11.3   -2.074   0.217  0.0000    1.0     8.00       966  0.800
  43    0.0 2.1e-04   1.000       4.60 3.6242e-09   2.074      -11.3   -2.074   0.043  0.0000    1.0     8.00       989  0.950
  44    0.0 0.0e+00   1.000       4.60 3.6242e-09   2.074      -11.3   -2.074   0.130  0.0000    1.0     8.00      1012  0.800
## Placement Quench took 0.00 seconds (max_rss 64.3 MiB)
post-quench CPD = 2.07439 (ns) 

Completed placement consistency check successfully.

Swaps called: 1030

Aborted Move Reasons:
  No moves aborted

BB estimate of min-dist (placement) wire length: 86

Placement estimated critical path delay (least slack): 2.07439 ns, Fmax: 482.069 MHz
Placement estimated setup Worst Negative Slack (sWNS): -2.07439 ns
Placement estimated setup Total Negative Slack (sTNS): -11.3066 ns

Placement estimated setup slack histogram:
[ -2.1e-09:   -2e-09) 1 ( 12.5%) |****************
[   -2e-09: -1.8e-09) 0 (  0.0%) |
[ -1.8e-09: -1.7e-09) 2 ( 25.0%) |*********************************
[ -1.7e-09: -1.6e-09) 0 (  0.0%) |
[ -1.6e-09: -1.5e-09) 2 ( 25.0%) |*********************************
[ -1.5e-09: -1.3e-09) 0 (  0.0%) |
[ -1.3e-09: -1.2e-09) 0 (  0.0%) |
[ -1.2e-09: -1.1e-09) 0 (  0.0%) |
[ -1.1e-09: -9.8e-10) 0 (  0.0%) |
[ -9.8e-10: -8.6e-10) 3 ( 37.5%) |*************************************************

Placement estimated geomean non-virtual intra-domain period: nan ns (nan MHz)
Placement estimated fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz)

Placement cost: 1, bb_cost: 4.5957, td_cost: 3.62421e-09, 

Placement resource usage:
  io  implemented as io : 16
  clb implemented as clb: 2

Placement number of temperatures: 44
Placement total # of swap attempts: 1030
	Swaps accepted:  311 (30.2 %)
	Swaps rejected:  719 (69.8 %)
	Swaps aborted:    0 ( 0.0 %)


Placement perturbation distribution by block and move type: 
------------------ ----------------- ---------------- ---------------- --------------- ------------ 
    Block Type         Move Type       (%) of Total      Accepted(%)     Rejected(%)    Aborted(%)
------------------ ----------------- ---------------- ---------------- --------------- ------------ 
io                 Uniform                24.08            35.48           64.52          0.00         
                   Median                 17.86            28.80           71.20          0.00         
                   Centroid               16.60            39.18           60.82          0.00         
                   W. Centroid            21.07            38.71           61.29          0.00         
                   W. Median              3.40             11.43           88.57          0.00         
                   Crit. Uniform          1.84             21.05           78.95          0.00         
                   Feasible Region        2.62             37.04           62.96          0.00         

clb                Uniform                2.04             0.00            100.00         0.00         
                   Median                 1.17             8.33            91.67          0.00         
                   Centroid               2.04             0.00            100.00         0.00         
                   W. Centroid            1.75             0.00            100.00         0.00         
                   W. Median              0.78             0.00            100.00         0.00         
                   Crit. Uniform          1.84             0.00            100.00         0.00         
                   Feasible Region        2.91             0.00            100.00         0.00         


Placement Quench timing analysis took 2.9278e-05 seconds (2.6119e-05 STA, 3.159e-06 slack) (1 full updates: 1 setup, 0 hold, 0 combined).
Placement Total  timing analysis took 0.00162369 seconds (0.00146333 STA, 0.000160366 slack) (46 full updates: 46 setup, 0 hold, 0 combined).
update_td_costs: connections 0 nets 0 sum_nets 0 total 0
# Placement took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

# Routing
RR graph channel widths unchanged, skipping RR graph rebuild
## Initializing router criticalities
Initial Net Connection Criticality Histogram:
[        0:      0.1)  0 (  0.0%) |
[      0.1:      0.2)  0 (  0.0%) |
[      0.2:      0.3)  0 (  0.0%) |
[      0.3:      0.4)  0 (  0.0%) |
[      0.4:      0.5)  5 ( 14.7%) |********************
[      0.5:      0.6)  0 (  0.0%) |
[      0.6:      0.7)  0 (  0.0%) |
[      0.7:      0.8)  7 ( 20.6%) |****************************
[      0.8:      0.9) 10 ( 29.4%) |****************************************
[      0.9:        1) 12 ( 35.3%) |************************************************
## Initializing router criticalities took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
Iter   Time    pres  BBs    Heap  Re-Rtd  Re-Rtd Overused RR Nodes      Wirelength      CPD       sTNS       sWNS       hTNS       hWNS Est Succ
      (sec)     fac Updt    push    Nets   Conns                                       (ns)       (ns)       (ns)       (ns)       (ns)     Iter
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
   1    0.0     0.0    0     622      26      34      25 ( 3.360%)     103 (42.9%)    2.473     -13.88     -2.473      0.000      0.000      N/A
Incr Slack updates 46 in 3.3579e-05 sec
Full Max Req/Worst Slack updates 3 in 2.879e-06 sec
Incr Max Req/Worst Slack updates 43 in 1.9945e-05 sec
Incr Criticality updates 40 in 7.2196e-05 sec
Full Criticality updates 6 in 1.1864e-05 sec
   2    0.0     0.5    0     514      20      27      17 ( 2.285%)     102 (42.5%)    2.473     -13.82     -2.473      0.000      0.000      N/A
   3    0.0     0.6    0     455      13      17      19 ( 2.554%)     110 (45.8%)    2.473     -14.19     -2.473      0.000      0.000      N/A
   4    0.0     0.8    0     472      14      19      15 ( 2.016%)     110 (45.8%)    2.473     -14.18     -2.473      0.000      0.000      N/A
   5    0.0     1.1    0     471      13      18      13 ( 1.747%)     116 (48.3%)    2.473     -14.42     -2.473      0.000      0.000      N/A
   6    0.0     1.4    0     354      13      19      13 ( 1.747%)     120 (50.0%)    2.473     -14.50     -2.473      0.000      0.000      N/A
   7    0.0     1.9    0     430      13      19      11 ( 1.478%)     121 (50.4%)    2.473     -14.63     -2.473      0.000      0.000      N/A
   8    0.0     2.4    0     380      12      17      10 ( 1.344%)     115 (47.9%)    2.473     -14.38     -2.473      0.000      0.000      N/A
   9    0.0     3.1    0     275       9      13       3 ( 0.403%)     128 (53.3%)    2.471     -15.09     -2.471      0.000      0.000      N/A
  10    0.0     4.1    0     209       5       7       2 ( 0.269%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       14
  11    0.0     5.3    0     192       5       7       3 ( 0.403%)     129 (53.8%)    2.471     -15.25     -2.471      0.000      0.000       12
  12    0.0     6.9    0     176       4       6       2 ( 0.269%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       13
  13    0.0     9.0    0     246       6       8       3 ( 0.403%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       13
  14    0.0    11.6    0     197       4       5       3 ( 0.403%)     122 (50.8%)    2.471     -14.85     -2.471      0.000      0.000       15
  15    0.0    15.1    0     173       3       4       2 ( 0.269%)     130 (54.2%)    2.471     -15.25     -2.471      0.000      0.000       20
  16    0.0    19.7    0     388       6       8       4 ( 0.538%)     147 (61.2%)    2.471     -16.00     -2.471      0.000      0.000       20
  17    0.0    25.6    0     153       5       6       2 ( 0.269%)     133 (55.4%)    2.526     -15.50     -2.526      0.000      0.000      inf
  18    0.0    33.3    0     106       5       7       1 ( 0.134%)     137 (57.1%)    2.645     -15.62     -2.645      0.000      0.000      inf
  19    0.0    43.3    0     108       5       7       2 ( 0.269%)     133 (55.4%)    2.663     -15.63     -2.663      0.000      0.000       31
  20    0.0    56.2    0     108       4       6       1 ( 0.134%)     133 (55.4%)    2.529     -15.51     -2.529      0.000      0.000       33
  21    0.0    73.1    0     219       5       7       2 ( 0.269%)     138 (57.5%)    2.529     -15.83     -2.529      0.000      0.000       23
  22    0.0    95.0    0      84       3       5       1 ( 0.134%)     133 (55.4%)    2.529     -15.51     -2.529      0.000      0.000       26
  23    0.0   123.5    0     128       4       6       1 ( 0.134%)     134 (55.8%)    2.665     -15.64     -2.665      0.000      0.000       24
  24    0.0   160.6    0     148       4       6       1 ( 0.134%)     134 (55.8%)    2.665     -15.64     -2.665      0.000      0.000       24
  25    0.0   208.8    0     146       4       6       3 ( 0.403%)     139 (57.9%)    2.935     -15.91     -2.935      0.000      0.000       23
  26    0.0   271.4    0     112       4       6       1 ( 0.134%)     133 (55.4%)    2.529     -15.51     -2.529      0.000      0.000       27
  27    0.0   352.8    0     213       5       7       2 ( 0.269%)     141 (58.7%)    3.031     -16.01     -3.031      0.000      0.000       27
  28    0.0   458.7    0     181       4       6       1 ( 0.134%)     134 (55.8%)    2.665     -15.64     -2.665      0.000      0.000       31
  29    0.0   596.3    0     140       4       6       2 ( 0.269%)     142 (59.2%)    3.165     -16.14     -3.165      0.000      0.000       31
  30    0.0   775.1    0     133       4       6       3 ( 0.403%)     143 (59.6%)    3.165     -16.30     -3.165      0.000      0.000       38
  31    0.0  1000.0    0     192       6       9       2 ( 0.269%)     151 (62.9%)    2.935     -16.69     -2.935      0.000      0.000      132
  32    0.0  1000.0    0     196       6       8       3 ( 0.403%)     152 (63.3%)    3.009     -16.97     -3.009      0.000      0.000      inf
  33    0.0  1000.0    0     204       5       7       1 ( 0.134%)     141 (58.7%)    2.935     -16.15     -2.935      0.000      0.000       12
  34    0.0  1000.0    0     210       5       7       0 ( 0.000%)     145 (60.4%)    2.935     -16.34     -2.935      0.000      0.000        5
Restoring best routing
Critical path: 2.93509 ns
Successfully routed after 34 routing iterations.
Final Net Connection Criticality Histogram:
[        0:      0.1)  0 (  0.0%) |
[      0.1:      0.2)  0 (  0.0%) |
[      0.2:      0.3)  0 (  0.0%) |
[      0.3:      0.4)  1 (  2.9%) |***
[      0.4:      0.5)  2 (  5.9%) |******
[      0.5:      0.6)  3 (  8.8%) |*********
[      0.6:      0.7)  1 (  2.9%) |***
[      0.7:      0.8)  5 ( 14.7%) |***************
[      0.8:      0.9)  6 ( 17.6%) |******************
[      0.9:        1) 16 ( 47.1%) |************************************************
Router Stats: total_nets_routed: 248 total_connections_routed: 346 total_heap_pushes: 8335 total_heap_pops: 5679 
Serial Connection Router is being destroyed. Time spent on path search: 0.000 seconds.
# Routing took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Checking to ensure routing is legal...
# Checking to ensure non-configurable edges are legal
# Checking to ensure non-configurable edges are legal took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Completed routing consistency check successfully.

Serial number (magic cookie) for the routing is: -1300952
Circuit successfully routed with a channel width factor of 20.
Warning 6: Synchronization between packing and routing results was not applied due to skip_sync_clustering_and_routing_results being set to true
Final Clustering Statistics: 
----------   --------   ------------------------------------   --------------------------
Block Type   # Blocks   Avg. # of input clocks and pins used   Avg. # of output pins used
----------   --------   ------------------------------------   --------------------------
     EMPTY          0                                      0                            0   
        io         16                                    0.5                          0.5   
       clb          2                                     13                            9   
Absorbed logical nets 3 out of 29 nets, 26 nets not absorbed.


Average number of bends per net: 2.50000  Maximum # of bends: 14

Number of global nets: 0
Number of routed nets (nonglobal): 26
Wire length results (in units of 1 clb segments)...
	Total wirelength: 145, average net length: 5.57692
	Maximum net length: 23

Wire length results in terms of physical segments...
	Total wiring segments used: 94, average wire segments per net: 3.61538
	Maximum segments used by a net: 15
	Total local nets with reserved CLB opins: 0
Total number of nets absorbed: 0

Routing channel utilization histogram:
[        1:      inf) 0 (  0.0%) |
[      0.9:        1) 0 (  0.0%) |
[      0.8:      0.9) 0 (  0.0%) |
[      0.7:      0.8) 5 ( 27.8%) |*****************************************
[      0.5:      0.6) 6 ( 33.3%) |*************************************************
[      0.4:      0.5) 0 (  0.0%) |
[      0.3:      0.4) 1 (  5.6%) |********
[      0.2:      0.3) 0 (  0.0%) |
[      0.1:      0.2) 0 (  0.0%) |
[        0:      0.1) 6 ( 33.3%) |*************************************************
Maximum routing channel utilization:      0.75 at (2,0)

X - Directed channels: layer   y   max occ   ave occ   ave cap
                        ----- ---- -------- -------- --------
                            0    0       15   13.500       20
                            0    1       13   13.000       20
                            0    2       13   12.500       20
Y - Directed channels: layer   x   max occ   ave occ   ave cap
                        ----- ---- -------- -------- --------
                            0    0       12   11.500       20
                            0    1       11    9.500       20
                            0    2       13   12.500       20

Total existing wires segments: CHANX 78, CHANY 67, ALL 145
Total used wires segments:     CHANX 78, CHANY 67, ALL 145
Usage percentage:               CHANX 0%, CHANY -1%, ALL 462506247%

Logic area (in minimum width transistor areas, excludes I/Os and empty grid tiles)...
	Total logic block area (Warning, need to add pitch of routing to blocks with height > 3): 215576
	Total used logic block area: 107788

Routing area (in minimum width transistor areas)...
	Total routing area: 12917.9, per logic tile: 807.366

Total Number of Wiring Segments by Direction: direction length number
                                              --------- ------ -------
                                                      X      4     78
                                                      Y      4     78

X - Directed Wiring Segment usage by length: length utilization
                                             ------ -----------
                                             4       0.628

Y - Directed Wiring Segment usage by length: length utilization
                                             ------ -----------
                                             4       0.577

Segment occupancy by length: Length Occupancy Capacity Utilization
                             ------ --------- -------- -----------
                             L4            94      156       0.603

Segment occupancy by type: name type utilization
                           ---- ---- -----------
                             L4    0       0.603

Final hold Worst Negative Slack (hWNS): 0 ns
Final hold Total Negative Slack (hTNS): 0 ns

Final hold slack histogram:
[  8.3e-10:  9.5e-10) 3 ( 37.5%) |*************************************************
[  9.5e-10:  1.1e-09) 1 ( 12.5%) |****************
[  1.1e-09:  1.2e-09) 1 ( 12.5%) |****************
[  1.2e-09:  1.3e-09) 0 (  0.0%) |
[  1.3e-09:  1.4e-09) 2 ( 25.0%) |*********************************
[  1.4e-09:  1.5e-09) 0 (  0.0%) |
[  1.5e-09:  1.7e-09) 0 (  0.0%) |
[  1.7e-09:  1.8e-09) 0 (  0.0%) |
[  1.8e-09:  1.9e-09) 0 (  0.0%) |
[  1.9e-09:    2e-09) 1 ( 12.5%) |****************

Final critical path delay (least slack): 2.93509 ns, Fmax: 340.705 MHz
Final setup Worst Negative Slack (sWNS): -2.93509 ns
Final setup Total Negative Slack (sTNS): -16.3447 ns

Final setup slack histogram:
[ -2.9e-09: -2.8e-09) 1 ( 12.5%) |*************************
[ -2.8e-09: -2.6e-09) 1 ( 12.5%) |*************************
[ -2.6e-09: -2.4e-09) 0 (  0.0%) |
[ -2.4e-09: -2.3e-09) 1 ( 12.5%) |*************************
[ -2.3e-09: -2.1e-09) 0 (  0.0%) |
[ -2.1e-09: -1.9e-09) 2 ( 25.0%) |*************************************************
[ -1.9e-09: -1.8e-09) 0 (  0.0%) |
[ -1.8e-09: -1.6e-09) 1 ( 12.5%) |*************************
[ -1.6e-09: -1.4e-09) 0 (  0.0%) |
[ -1.4e-09: -1.3e-09) 2 ( 25.0%) |*************************************************

Final geomean non-virtual intra-domain period: nan ns (nan MHz)
Final fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz)

Incr Slack updates 1 in 1.144e-06 sec
Full Max Req/Worst Slack updates 1 in 8.5e-07 sec
Incr Max Req/Worst Slack updates 0 in 0 sec
Incr Criticality updates 0 in 0 sec
Full Criticality updates 1 in 2.532e-06 sec
Flow timing analysis took 0.00434245 seconds (0.00382115 STA, 0.000521303 slack) (83 full updates: 47 setup, 0 hold, 36 combined).
VPR succeeded
The entire flow of VPR took 0.06 seconds (max_rss 64.3 MiB)

Command line to execute: read_openfpga_arch -f /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run067/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_40nm_openfpga.xml

Confirm selected options when call command 'read_openfpga_arch':
--file, -f: /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run067/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_40nm_openfpga.xml
Reading XML architecture '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/run067/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/arch/k6_frac_N10_40nm_openfpga.xml'...
Read OpenFPGA architecture
Warning 7: Automatically set circuit model 'frac_lut6' to be default in its type.
Warning 8: Automatically set circuit model 'DFFSRQ' to be default in its type.
Warning 9: Automatically set circuit model 'DFFR' to be default in its type.
Warning 10: Automatically set circuit model 'GPIO' to be default in its type.
Use the default configurable memory model 'DFFR' for circuit model 'mux_2level' port 'sram')
Use the default configurable memory model 'DFFR' for circuit model 'mux_2level_tapbuf' port 'sram')
Use the default configurable memory model 'DFFR' for circuit model 'mux_1level_tapbuf' port 'sram')
Use the default configurable memory model 'DFFR' for circuit model 'frac_lut6' port 'sram')
Read OpenFPGA architecture took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Check circuit library
Checking circuit library passed.
Check circuit library took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Found 0 errors when checking configurable memory circuit models!
Found 0 errors when checking configuration protocol!
Found 0 errors when checking tile annotation!

Command line to execute: read_openfpga_simulation_setting -f /home/moshida/OpenFPGA/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml

Confirm selected options when call command 'read_openfpga_simulation_setting':
--file, -f: /home/moshida/OpenFPGA/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Reading XML simulation setting '/home/moshida/OpenFPGA/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
Read OpenFPGA simulation settings
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: link_openfpga_arch --activity_file mult4_ace_out.act --sort_gsb_chan_node_in_edges

Confirm selected options when call command 'link_openfpga_arch':
--activity_file: mult4_ace_out.act
--sort_gsb_chan_node_in_edges: on
--verbose: off
Link OpenFPGA architecture to VPR architecture
# Build fast look-up for physical tile pins
# Build fast look-up for physical tile pins took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Building annotation for physical modes in pb_type...Done
Check physical mode annotation for pb_types passed.

Building annotation about physical types for pb_type interconnection...Done

Building annotation between operating and physical pb_types...Done
Check physical pb_type annotation for pb_types passed.

Building annotation between physical pb_types and circuit models...Done
Check physical pb_type annotation for circuit model passed.

Building annotation between physical pb_types and mode selection bits...Done
Check pb_type annotation for mode selection bits passed.
Assigning unique indices for primitive pb_graph nodes...Done
Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...Done
Check pb_graph annotation for physical nodes and pins passed.
Binded 2 routing resource graph switches to circuit models
Binded 1 routing segments to circuit models
Binded 0 direct connections to circuit models
# Annotating rr_node with routed nets
# Annotating rr_node with routed nets took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Loaded node-to-net mapping
Annotating previous nodes for rr_node...Warning 11: Override the previous node 'IPIN:467 side: (RIGHT,) (2,2,0)' by previous node 'IPIN:466 side: (RIGHT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 12: Override the previous node 'IPIN:466 side: (RIGHT,) (2,2,0)' by previous node 'IPIN:483 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 13: Override the previous node 'IPIN:245 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:249 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 14: Override the previous node 'IPIN:483 side: (LEFT,) (2,2,0)' by previous node 'IPIN:451 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 15: Override the previous node 'IPIN:249 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:261 side: (LEFT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 16: Override the previous node 'IPIN:261 side: (LEFT,) (2,1,0)' by previous node 'IPIN:223 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 17: Override the previous node 'IPIN:451 side: (TOP,) (2,2,0)' by previous node 'IPIN:452 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 18: Override the previous node 'IPIN:452 side: (TOP,) (2,2,0)' by previous node 'IPIN:489 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 19: Override the previous node 'IPIN:223 side: (TOP,) (2,1,0)' by previous node 'IPIN:224 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 20: Override the previous node 'IPIN:489 side: (LEFT,) (2,2,0)' by previous node 'IPIN:484 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 21: Override the previous node 'IPIN:224 side: (TOP,) (2,1,0)' by previous node 'IPIN:246 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 22: Override the previous node 'IPIN:484 side: (LEFT,) (2,2,0)' by previous node 'IPIN:454 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 23: Override the previous node 'IPIN:246 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:244 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 24: Override the previous node 'IPIN:454 side: (TOP,) (2,2,0)' by previous node 'IPIN:482 side: (LEFT,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 25: Override the previous node 'IPIN:244 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:243 side: (BOTTOM,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 26: Override the previous node 'IPIN:482 side: (LEFT,) (2,2,0)' by previous node 'IPIN:455 side: (TOP,) (2,2,0)' for node 'SINK:429  (2,2,0)' with in routing context annotation!
Warning 27: Override the previous node 'IPIN:243 side: (BOTTOM,) (2,1,0)' by previous node 'IPIN:226 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 28: Override the previous node 'IPIN:226 side: (TOP,) (2,1,0)' by previous node 'IPIN:233 side: (RIGHT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 29: Override the previous node 'IPIN:233 side: (RIGHT,) (2,1,0)' by previous node 'IPIN:221 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 30: Override the previous node 'IPIN:221 side: (TOP,) (2,1,0)' by previous node 'IPIN:222 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 31: Override the previous node 'IPIN:222 side: (TOP,) (2,1,0)' by previous node 'IPIN:254 side: (LEFT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 32: Override the previous node 'IPIN:254 side: (LEFT,) (2,1,0)' by previous node 'IPIN:235 side: (RIGHT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 33: Override the previous node 'IPIN:235 side: (RIGHT,) (2,1,0)' by previous node 'IPIN:230 side: (TOP,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Warning 34: Override the previous node 'IPIN:230 side: (TOP,) (2,1,0)' by previous node 'IPIN:236 side: (RIGHT,) (2,1,0)' for node 'SINK:199  (2,1,0)' with in routing context annotation!
Done with 0 nodes mapping
Built 1732 incoming edges for routing resource graph
# Build General Switch Block(GSB) annotation on top of routing resource graph
[11%] Backannotated GSB[0][0]
[22%] Backannotated GSB[0][1]
[33%] Backannotated GSB[0][2]
[44%] Backannotated GSB[1][0]
[55%] Backannotated GSB[1][1]
[66%] Backannotated GSB[1][2]
[77%] Backannotated GSB[2][0]
[88%] Backannotated GSB[2][1]
[100%] Backannotated GSB[2][2]
Backannotated 9 General Switch Blocks (GSBs).
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
[11%] Sorted incoming edges for each routing track output node of GSB[0][0]
[22%] Sorted incoming edges for each routing track output node of GSB[0][1]
[33%] Sorted incoming edges for each routing track output node of GSB[0][2]
[44%] Sorted incoming edges for each routing track output node of GSB[1][0]
[55%] Sorted incoming edges for each routing track output node of GSB[1][1]
[66%] Sorted incoming edges for each routing track output node of GSB[1][2]
[77%] Sorted incoming edges for each routing track output node of GSB[2][0]
[88%] Sorted incoming edges for each routing track output node of GSB[2][1]
[100%] Sorted incoming edges for each routing track output node of GSB[2][2]
Sorted incoming edges for each routing track output node of 9 General Switch Blocks (GSBs).
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each input pin node of General Switch Block(GSB)
[11%] Sorted incoming edges for each input pin node of GSB[0][0]
[22%] Sorted incoming edges for each input pin node of GSB[0][1]
[33%] Sorted incoming edges for each input pin node of GSB[0][2]
[44%] Sorted incoming edges for each input pin node of GSB[1][0]
[55%] Sorted incoming edges for each input pin node of GSB[1][1]
[66%] Sorted incoming edges for each input pin node of GSB[1][2]
[77%] Sorted incoming edges for each input pin node of GSB[2][0]
[88%] Sorted incoming edges for each input pin node of GSB[2][1]
[100%] Sorted incoming edges for each input pin node of GSB[2][2]
Sorted incoming edges for each input pin node of 9 General Switch Blocks (GSBs).
# Sort incoming edges for each input pin node of General Switch Block(GSB) took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build a library of physical multiplexers
Built a multiplexer library of 12 physical multiplexers.
Maximum multiplexer size is 64.
	model 'mux_2level_tapbuf', input_size='5'
	model 'mux_2level_tapbuf', input_size='3'
	model 'mux_2level_tapbuf', input_size='4'
	model 'mux_2level_tapbuf', input_size='10'
	model 'mux_2level_tapbuf', input_size='8'
	model 'mux_2level_tapbuf', input_size='9'
	model 'mux_2level_tapbuf', input_size='12'
	model 'mux_2level_tapbuf', input_size='11'
	model 'mux_2level_tapbuf', input_size='6'
	model 'mux_2level', input_size='61'
	model 'mux_1level_tapbuf', input_size='3'
	model 'frac_lut6', input_size='64'
# Build a library of physical multiplexers took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build the annotation about direct connection between tiles
Built 0 tile-to-tile direct connections
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Building annotation for post-routing and clustering synchornization results...Done
Building annotation for mapped blocks on grid locations...Done
User specified the operating clock frequency to use VPR results
Use VPR critical path delay 3.52211e-18 [ns] with a 20 [%] slack in OpenFPGA.
Incr Slack updates 1 in 6.957e-06 sec
Full Max Req/Worst Slack updates 1 in 2.715e-06 sec
Incr Max Req/Worst Slack updates 0 in 0 sec
Incr Criticality updates 0 in 0 sec
Full Criticality updates 1 in 8.281e-06 sec
Will apply operating clock frequency 283.921 [MHz] to simulations
User specified the number of operating clock cycles to be inferred from signal activities
Average net density: 0.08
Median net density: 0.00
Average net density after weighting: 0.13
Will apply 12 operating clock cycles to simulations
Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

Confirm selected options when call command 'check_netlist_naming_conflict':
--fix: on
--report: ./netlist_renaming.xml
Check naming violations of netlist blocks and nets
Fixed 66 naming conflicts in the netlist.
Naming fix-up report is generated to file './netlist_renaming.xml'
Check naming violations of netlist blocks and nets took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: build_fabric --compress_routing

Confirm selected options when call command 'build_fabric':
--frame_view: off
--compress_routing: on
--duplicate_grid_pin: off
--name_module_using_index: off
--load_fabric_key: off
--write_fabric_key: off
--group_tile: off
--group_config_block: off
--generate_random_fabric_key: off
--verbose: off
Identify unique General Switch Blocks (GSBs)
Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%)
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)


Build fabric module graph
# Build constant generator modules
# Build constant generator modules took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build user-defined modules
# Build user-defined modules took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build essential (inverter/buffer/logic gate) modules
# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build local encoder (for multiplexers) modules
# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Building multiplexer modules
# Building multiplexer modules took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build Look-Up Table (LUT) modules
# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build wire modules
# Build wire modules took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build memory modules
# Build memory modules took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build grid modules
Building logical tiles...Done
Building physical tiles...Done
# Build grid modules took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build unique routing modules...
# Build unique routing modules... took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build FPGA fabric module
## Add grid instances to top module
## Add grid instances to top module took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
## Add switch block instances to top module
## Add switch block instances to top module took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
## Add module nets between grids and GSBs
## Add module nets between grids and GSBs took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
## Add module nets for inter-tile connections
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
## Build configurable regions for the top module
## Build configurable regions for the top module took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
## Add module nets for configuration buses
## Add module nets for configuration buses took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
# Build FPGA fabric module took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Build fabric module graph took 0.01 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Create I/O location mapping for top module
Create I/O location mapping for top module took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Create global port info for top module
Create global port info for top module took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: repack --verbose

Confirm selected options when call command 'repack':
--design_constraints: off
--ignore_global_nets_on_pins: off
--verbose: on
Build routing resource graph for the physical implementation of logical tile
Building routing resource graph for logical tile 'io'...
	Number of nodes: 8
	Number of edges: 7
Check routing resource graph for logical tile passed
Building routing resource graph for logical tile 'clb'...
	Number of nodes: 574
	Number of edges: 4153
Check routing resource graph for logical tile passed
Done
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Repack clustered blocks to physical implementation of logical tile
Repack clustered block 'new_$abc$328$new_n22'...
Follow the same mapping results for net 'A[2]' on pin 'I[0]' during repacking (constrained net name is )
Pb route for Net A[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[0] -> clb[0].I[0]
Sink nodes:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[3]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[3]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[1]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[2]' during repacking (constrained net name is )
Follow the same mapping results for net 'new_$abc$328$new_n27' on pin 'I[3]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n27:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[3] -> clb[0].I[3]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[3]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[3]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[3]' on pin 'I[4]' during repacking (constrained net name is )
Pb route for Net A[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[4] -> clb[0].I[4]
Sink nodes:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[2]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[2]' on pin 'I[5]' during repacking (constrained net name is )
Pb route for Net B[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[5] -> clb[0].I[5]
Sink nodes:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[4]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[1]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[6]' during repacking (constrained net name is )
Pb route for Net A[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[6] -> clb[0].I[6]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[3]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[1]' on pin 'I[7]' during repacking (constrained net name is )
Pb route for Net A[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[7] -> clb[0].I[7]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[0]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[1]' on pin 'I[8]' during repacking (constrained net name is )
Pb route for Net B[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[8] -> clb[0].I[8]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[4]
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[0]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[0]' on pin 'I[9]' during repacking (constrained net name is )
Pb route for Net B[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[9] -> clb[0].I[9]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[1]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n25' on pin 'I[10]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n25:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[10] -> clb[0].I[10]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[3]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[3]' on pin 'I[11]' during repacking (constrained net name is )
Pb route for Net B[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[11] -> clb[0].I[11]
Sink nodes:
	clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[1]
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[1]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[12]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[13]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[14]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[15]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[16]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[17]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[18]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[19]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[20]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[21]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[22]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[23]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[24]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[25]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[26]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[27]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[28]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[29]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[30]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[31]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[32]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[33]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[34]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[35]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[36]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[37]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[38]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[39]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'clk[0]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n35:
Source node:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[0]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[3]
Pb route for Net new_$abc$328$new_n26:
Source node:
	clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[1]
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[0]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[3]
Pb route for Net Y[1]:
Source node:
	clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[11]
Pb route for Net new_$abc$328$new_n30:
Source node:
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[2]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[1]
Pb route for Net new_$abc$328$new_n33:
Source node:
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[12]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[2]
Pb route for Net new_$abc$328$new_n32:
Source node:
	clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[2]
Pb route for Net new_$abc$328$new_n36:
Source node:
	clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[13]
	clb[0]/fle[4]/ble6[0]/lut6[0].in[5]
Pb route for Net Y[6]:
Source node:
	clb[0]/fle[4]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[4]
Pb route for Net new_$abc$328$new_n31:
Source node:
	clb[0]/fle[5]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[1]
	clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[1]
Pb route for Net new_$abc$328$new_n24:
Source node:
	clb[0]/fle[6]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[6]
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[2]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[2]
Pb route for Net new_$abc$328$new_n23:
Source node:
	clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[7]
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[1]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[1]
Pb route for Net Y[5]:
Source node:
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[17]
Pb route for Net new_$abc$328$new_n29:
Source node:
	clb[0]/fle[8]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[0]
Pb route for Net new_$abc$328$new_n22:
Source node:
	clb[0]/fle[9]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[9]
	clb[0]/fle[8]/ble6[0]/lut6[0].in[5]
Added 24 nets to be routed.
Reroute succeed
Update physical pb 'clb[0][default]/fle[0][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n35'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[0][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[1][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n26'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[1][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[1][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[1]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[1][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[1]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[2][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n30'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[2][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[2][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n33'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[2][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[2]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[3][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n32'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[3][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[3][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n36'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[3][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[3]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[4][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[6]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[4][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[5][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n31'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[5][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[6][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n24'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[6][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[3]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[4]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[7][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n23'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[7][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[7][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[5]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[7][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[8][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n29'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[8][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[4]'...
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Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[9][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n22'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[9][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Save net 'A[2]' to physical pb_graph_pin 'clb[0].I[0]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[4]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[4]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0].I[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8].in[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0].I[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0].I[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0].I[6]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9].in[5]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[5]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0].I[7]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0].I[8]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[3]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[3]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0].I[9]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0].I[10]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8].in[4]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0].I[11]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[0].out[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0].O[0]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4].in[3]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[1].out[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0].O[1]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0]/frac_logic[0].out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1]/fabric[0].out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0]/fle[1].out[1]'
Save net 'Y[1]' to physical pb_graph_pin 'clb[0].O[11]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[2].out[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0].O[2]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7].in[1]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[2].out[1]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0].O[12]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[3].out[0]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n32' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0]/frac_logic[0].out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3]/fabric[0].out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[3].out[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0].O[13]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4].in[5]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0]/fle[4].out[0]'
Save net 'Y[6]' to physical pb_graph_pin 'clb[0].O[4]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[5].out[0]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2].in[1]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n31' to physical pb_graph_pin 'clb[0]/fle[2]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[6].out[0]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0].O[6]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7].out[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0].O[7]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0]/fle[7].out[1]'
Save net 'Y[5]' to physical pb_graph_pin 'clb[0].O[17]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[8].out[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7].in[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n29' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[9].out[0]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0].O[9]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8].in[5]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Saved results in physical pb
Done
Repack clustered block 'new_$abc$328$new_n25'...
Follow the same mapping results for net 'A[2]' on pin 'I[0]' during repacking (constrained net name is )
Pb route for Net A[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[0] -> clb[0].I[0]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[3]' on pin 'I[1]' during repacking (constrained net name is )
Pb route for Net A[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[1] -> clb[0].I[1]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[1]' on pin 'I[2]' during repacking (constrained net name is )
Pb route for Net A[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[2] -> clb[0].I[2]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n23' on pin 'I[3]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n23:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[3] -> clb[0].I[3]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n26' on pin 'I[4]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n26:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[4] -> clb[0].I[4]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n30' on pin 'I[5]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n30:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[5] -> clb[0].I[5]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[5]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n35' on pin 'I[6]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n35:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[6] -> clb[0].I[6]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[3]' on pin 'I[7]' during repacking (constrained net name is )
Pb route for Net B[3]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[7] -> clb[0].I[7]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[0]' on pin 'I[8]' during repacking (constrained net name is )
Pb route for Net B[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[8] -> clb[0].I[8]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[1]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[2]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[1]' on pin 'I[9]' during repacking (constrained net name is )
Pb route for Net B[1]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[9] -> clb[0].I[9]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[2]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'B[2]' on pin 'I[10]' during repacking (constrained net name is )
Pb route for Net B[2]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[10] -> clb[0].I[10]
Sink nodes:
	clb[0]/fle[5]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[6]/ble6[0]/lut6[0].in[4]
	clb[0]/fle[9]/ble6[0]/lut6[0].in[1]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n24' on pin 'I[11]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n24:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[11] -> clb[0].I[11]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[5]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[4]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n22' on pin 'I[12]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n22:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[12] -> clb[0].I[12]
Sink nodes:
	clb[0]/fle[7]/ble6[0]/lut6[0].in[3]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[3]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[13]' during repacking (constrained net name is )
Pb route for Net A[0]:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[13] -> clb[0].I[13]
Sink nodes:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]
	clb[0]/fle[5]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n33' on pin 'I[14]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n33:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[14] -> clb[0].I[14]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[0]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'new_$abc$328$new_n36' on pin 'I[15]' during repacking (constrained net name is )
Pb route for Net new_$abc$328$new_n36:
Search remapped routing traces for the unconstrained net
Source node:
	clb[0].I[15] -> clb[0].I[15]
Sink nodes:
	clb[0]/fle[4]/ble6[0]/lut6[0].in[1]
Append 0 sinks from the routing traces of ignored global nets
Follow the same mapping results for net 'A[0]' on pin 'I[16]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[17]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[18]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[19]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[20]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[21]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[22]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[23]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[24]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[25]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[26]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[27]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[28]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[29]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[30]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[31]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[32]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[33]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[34]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[35]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[36]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[37]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[38]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'I[39]' during repacking (constrained net name is )
Follow the same mapping results for net 'A[0]' on pin 'clk[0]' during repacking (constrained net name is )
Pb route for Net Y[0]:
Source node:
	clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0] -> clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]
Sink nodes:
	clb[0].O[0]
Pb route for Net Y[7]:
Source node:
	clb[0]/fle[4]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[4]
Pb route for Net Y[2]:
Source node:
	clb[0]/fle[5]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[5]
Pb route for Net new_$abc$328$new_n27:
Source node:
	clb[0]/fle[6]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[6]
	clb[0]/fle[7]/ble6[0]/lut6[0].in[1]
Pb route for Net Y[4]:
Source node:
	clb[0]/fle[7]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[7]
Pb route for Net Y[3]:
Source node:
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].out[0] -> clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]
Sink nodes:
	clb[0].O[18]
Pb route for Net new_$abc$328$new_n25:
Source node:
	clb[0]/fle[9]/ble6[0]/lut6[0].out[0] -> clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]
Sink nodes:
	clb[0].O[9]
	clb[0]/fle[7]/ble6[0]/lut6[0].in[0]
	clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[1]
Added 23 nets to be routed.
Reroute succeed
Update physical pb 'clb[0][default]/fle[0][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[0]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[0][n2_lut5]/lut5inter[0][default]/ble5[0][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[0]/lut5inter[0]/ble5[0]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[4][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[7]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[4][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[4]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[5][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[2]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[5][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[5]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[6][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n27'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[6][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[6]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[7][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[4]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[7][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[7]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[8][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'Y[3]'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[8][n2_lut5]/lut5inter[0][default]/ble5[1][default]/lut5[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[8]/lut5inter[0]/ble5[1]/lut5[0].out[0]'...
Skip due to empty model port
Update physical pb 'clb[0][default]/fle[9][physical]/fabric[0][default]/frac_logic[0][default]/frac_lut6[0]' using atom block 'new_$abc$328$new_n25'
Synchronizing atom nets on pb_graph_node 'clb[0][default]/fle[9][n1_lut6]/ble6[0][default]/lut6[0][]'...
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[0]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[1]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[2]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[3]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[4]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].in[5]'...
Skip due to empty model port
Synchronizing atom nets on pb_graph_pin 'clb[0]/fle[9]/ble6[0]/lut6[0].out[0]'...
Skip due to empty model port
Save net 'A[2]' to physical pb_graph_pin 'clb[0].I[0]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[3]'
Save net 'A[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0].I[1]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[5]'
Save net 'A[3]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0].I[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[4]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[4]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[4]'
Save net 'A[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0].I[3]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8].in[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n23' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0].I[4]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7].in[2]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n26' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0].I[5]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4].in[5]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n30' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0].I[6]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4].in[2]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[2]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[2]'
Save net 'new_$abc$328$new_n35' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0].I[7]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[3]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0].I[8]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[0]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0].I[9]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[2]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[0]'
Save net 'B[1]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0].I[10]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].in[1]'
Save net 'B[2]' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0].I[11]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[5]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8].in[4]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[4]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[4]'
Save net 'new_$abc$328$new_n24' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[4]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0].I[12]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[3]'
Save net 'new_$abc$328$new_n22' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[3]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0].I[13]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].in[0]'
Save net 'A[0]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0].I[14]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4].in[0]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n33' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0].I[15]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4].in[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n36' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0]/fabric[0].out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0]/fle[0].out[0]'
Save net 'Y[0]' to physical pb_graph_pin 'clb[0].O[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4]/fabric[0].out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0]/fle[4].out[0]'
Save net 'Y[7]' to physical pb_graph_pin 'clb[0].O[4]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5]/fabric[0].out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0]/fle[5].out[0]'
Save net 'Y[2]' to physical pb_graph_pin 'clb[0].O[5]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[6].out[0]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0].O[6]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7].in[1]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n27' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0]/fle[7].out[0]'
Save net 'Y[4]' to physical pb_graph_pin 'clb[0].O[7]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].lut5_out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0]/fle[8].out[1]'
Save net 'Y[3]' to physical pb_graph_pin 'clb[0].O[18]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0]/frac_lut6[0].lut6_out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0]/frac_logic[0].out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9]/fabric[0].out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[9].out[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0].O[9]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[7]/fabric[0]/frac_logic[0]/frac_lut6[0].in[0]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8].in[1]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0].in[1]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0].in[1]'
Save net 'new_$abc$328$new_n25' to physical pb_graph_pin 'clb[0]/fle[8]/fabric[0]/frac_logic[0]/frac_lut6[0].in[1]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[5]'...
Follow the same mapping results for net 'Y[5]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[5]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[5]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[5]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[5]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[5]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[6]'...
Follow the same mapping results for net 'Y[6]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[6]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[6]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[6]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[6]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[6]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[7]'...
Follow the same mapping results for net 'Y[7]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[7]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[7]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[7]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[7]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[7]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[4]'...
Follow the same mapping results for net 'Y[4]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[4]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[4]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[4]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[4]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[4]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[3]'...
Follow the same mapping results for net 'Y[3]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[3]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[3]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[3]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[3]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[3]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[2]'...
Follow the same mapping results for net 'Y[2]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[2]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[2]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[2]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[2]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[2]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[0]'...
Follow the same mapping results for net 'Y[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[0]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[0]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[0]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[0]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[0]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'out:Y[1]'...
Follow the same mapping results for net 'Y[1]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net Y[1]:
Search remapped routing traces for the unconstrained net
Source node:
	io[0].outpad[0] -> io[0].outpad[0]
Sink nodes:
	io[0]/iopad[0].outpad[0]
	io[0]/outpad[0].outpad[0]
Append 0 sinks from the routing traces of ignored global nets
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'out:Y[1]'
Synchronizing atom nets on pb_graph_node 'io[0][outpad]/outpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/outpad[0].outpad[0]'...
Synchronize net 'Y[1]' to physical pb_graph_pin 'io[0]/outpad[0].outpad[0]'
Save net 'Y[1]' to physical pb_graph_pin 'io[0].outpad[0]'
Save net 'Y[1]' to physical pb_graph_pin 'io[0]/iopad[0].outpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[0]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[0]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[0]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[0]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[0]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[0]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[1]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[1]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[1]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[1]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[1]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[1]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[2]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[2]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[2]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[2]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[2]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[2]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'A[3]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net A[3]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'A[3]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'A[3]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'A[3]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'A[3]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[0]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[0]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[0]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[0]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[0]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[0]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[1]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[1]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[1]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[1]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[1]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[1]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[2]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[2]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[2]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[2]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[2]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[2]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered block 'B[3]'...
Follow the same mapping results for net 'A[0]' on pin 'outpad[0]' during repacking (constrained net name is )
Pb route for Net B[3]:
Source node:
	io[0]/inpad[0].inpad[0] -> io[0]/iopad[0].inpad[0]
Sink nodes:
	io[0].inpad[0]
Added 1 nets to be routed.
Reroute succeed
Update physical pb 'io[0][physical]/iopad[0]' using atom block 'B[3]'
Synchronizing atom nets on pb_graph_node 'io[0][inpad]/inpad[0]'...
Synchronizing atom nets on pb_graph_pin 'io[0]/inpad[0].inpad[0]'...
Synchronize net 'B[3]' to physical pb_graph_pin 'io[0]/inpad[0].inpad[0]'
Save net 'B[3]' to physical pb_graph_pin 'io[0]/iopad[0].inpad[0]'
Save net 'B[3]' to physical pb_graph_pin 'io[0].inpad[0]'
Saved results in physical pb
Done
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Identify wire LUTs created by repacking
Identified 0 wire LUTs created by repacker
Identify wire LUTs created by repacking took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Build truth tables for physical LUTs
Build truth tables for physical LUTs under clustered block 'new_$abc$328$new_n22'...
Driver atom block: '33'
Pb atom blocks:'33', 
Input nets: new_$abc$328$new_n26  new_$abc$328$new_n23  new_$abc$328$new_n24  new_$abc$328$new_n25  new_$abc$328$new_n27  unconn  
Output net: new_$abc$328$new_n35
Truth table before adaption to fracturable LUT'
	-0-0-- 0
	-01--- 0
	--10-- 0
	0---0- 0
	1---1- 0
Add following truth table to pb_graph_pin 'lut5_out[0]'
	-0-0-1 0
	-01--1 0
	--10-1 0
	0---01 0
	1---11 0

Driver atom block: '24'
Pb atom blocks:'24', '17', 
Input nets: A[1]  B[0]  B[3]  A[0]  B[1]  unconn  
Output net: new_$abc$328$new_n26
Truth table before adaption to fracturable LUT'
	1-1--- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	1-1--1 1

Driver atom block: '17'
Pb atom blocks:'24', '17', 
Input nets: A[1]  B[0]  B[3]  A[0]  B[1]  unconn  
Output net: Y[1]
Truth table before adaption to fracturable LUT'
	0--11- 1
	-0-11- 1
	11-0-- 1
	11--0- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	0--110 1
	-0-110 1
	11-0-0 1
	11--00 1

Driver atom block: '28'
Pb atom blocks:'28', '31', 
Input nets: new_$abc$328$new_n26  new_$abc$328$new_n31  new_$abc$328$new_n32  new_$abc$328$new_n27  unconn  unconn  
Output net: new_$abc$328$new_n30
Truth table before adaption to fracturable LUT'
	-11--- 1
	1-11-- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	-11--1 1
	1-11-1 1

Driver atom block: '31'
Pb atom blocks:'28', '31', 
Input nets: new_$abc$328$new_n26  new_$abc$328$new_n31  new_$abc$328$new_n32  new_$abc$328$new_n27  unconn  unconn  
Output net: new_$abc$328$new_n33
Truth table before adaption to fracturable LUT'
	000--- 1
	-000-- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	000--0 1
	-000-0 1

Driver atom block: '30'
Pb atom blocks:'30', '34', 
Input nets: B[1]  B[3]  A[3]  A[2]  B[2]  unconn  
Output net: new_$abc$328$new_n32
Truth table before adaption to fracturable LUT'
	-101-- 1
	-1-10- 1
	--101- 1
	001-1- 1
	11-1-- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	-101-1 1
	-1-101 1
	--1011 1
	001-11 1
	11-1-1 1

Driver atom block: '34'
Pb atom blocks:'30', '34', 
Input nets: B[1]  B[3]  A[3]  A[2]  B[2]  unconn  
Output net: new_$abc$328$new_n36
Truth table before adaption to fracturable LUT'
	1-111- 0
	-1111- 0
Add following truth table to pb_graph_pin 'lut5_out[1]'
	1-1110 0
	-11110 0

Driver atom block: '32'
Pb atom blocks:'32', 
Input nets: new_$abc$328$new_n30  B[3]  new_$abc$328$new_n33  new_$abc$328$new_n35  A[3]  new_$abc$328$new_n36  
Output net: Y[6]
Truth table before adaption to fracturable LUT'
	1---01 1
	10---1 1
	11--10 1
	0--000 1
	00-0-0 1
	01-011 1
	--0101 1
	-001-1 1
	-10110 1
	0-1-00 1
	001--0 1
	011-11 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	1---01 1
	10---1 1
	11--10 1
	0--000 1
	00-0-0 1
	01-011 1
	--0101 1
	-001-1 1
	-10110 1
	0-1-00 1
	001--0 1
	011-11 1

Driver atom block: '29'
Pb atom blocks:'29', 
Input nets: A[1]  B[0]  B[2]  A[2]  B[1]  A[3]  
Output net: new_$abc$328$new_n31
Truth table before adaption to fracturable LUT'
	1-1110 1
	-10111 1
	111011 1
	111101 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	1-1110 1
	-10111 1
	111011 1
	111101 1

Driver atom block: '22'
Pb atom blocks:'22', 
Input nets: B[1]  A[1]  B[0]  B[2]  A[0]  A[2]  
Output net: new_$abc$328$new_n24
Truth table before adaption to fracturable LUT'
	11-11- 0
	--1111 0
	111--1 0
Add following truth table to pb_graph_pin 'lut6_out[0]'
	11-11- 0
	--1111 0
	111--1 0

Driver atom block: '21'
Pb atom blocks:'21', '26', 
Input nets: new_$abc$328$new_n29  new_$abc$328$new_n30  new_$abc$328$new_n33  B[3]  A[0]  unconn  
Output net: new_$abc$328$new_n23
Truth table before adaption to fracturable LUT'
	---11- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	---111 1

Driver atom block: '26'
Pb atom blocks:'21', '26', 
Input nets: new_$abc$328$new_n29  new_$abc$328$new_n30  new_$abc$328$new_n33  B[3]  A[0]  unconn  
Output net: Y[5]
Truth table before adaption to fracturable LUT'
	01---- 1
	100--- 1
	0-1--- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	01---0 1
	100--0 1
	0-1--0 1

Driver atom block: '27'
Pb atom blocks:'27', 
Input nets: new_$abc$328$new_n27  new_$abc$328$new_n23  new_$abc$328$new_n24  new_$abc$328$new_n26  new_$abc$328$new_n25  new_$abc$328$new_n22  
Output net: new_$abc$328$new_n29
Truth table before adaption to fracturable LUT'
	0-10-- 1
	1-11-- 1
	0--0-0 1
	1--1-0 1
	00-0-- 1
	10-1-- 1
	-01--0 1
	0--00- 1
	1--10- 1
	--1-00 1
	-01-0- 1
	-0--00 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	0-10-- 1
	1-11-- 1
	0--0-0 1
	1--1-0 1
	00-0-- 1
	10-1-- 1
	-01--0 1
	0--00- 1
	1--10- 1
	--1-00 1
	-01-0- 1
	-0--00 1

Driver atom block: '20'
Pb atom blocks:'20', 
Input nets: A[1]  B[2]  B[0]  B[1]  A[2]  A[0]  
Output net: new_$abc$328$new_n22
Truth table before adaption to fracturable LUT'
	101101 1
	111111 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	101101 1
	111111 1

Build truth tables for physical LUTs under clustered block 'new_$abc$328$new_n25'...
Driver atom block: '16'
Pb atom blocks:'16', 
Input nets: A[0]  unconn  unconn  unconn  B[0]  unconn  
Output net: Y[0]
Truth table before adaption to fracturable LUT'
	1---1- 1
Add following truth table to pb_graph_pin 'lut5_out[0]'
	1---11 1

Driver atom block: '36'
Pb atom blocks:'36', 
Input nets: new_$abc$328$new_n33  new_$abc$328$new_n36  new_$abc$328$new_n35  B[3]  A[3]  new_$abc$328$new_n30  
Output net: Y[7]
Truth table before adaption to fracturable LUT'
	-0-11- 1
	0-111- 1
	001--- 1
	---111 1
	-0---1 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	-0-11- 1
	0-111- 1
	001--- 1
	---111 1
	-0---1 1

Driver atom block: '18'
Pb atom blocks:'18', 
Input nets: A[0]  B[0]  A[1]  A[2]  B[1]  B[2]  
Output net: Y[2]
Truth table before adaption to fracturable LUT'
	00--0- 0
	000--- 0
	-0--00 0
	-00--0 0
	101-11 0
	0--00- 0
	0-00-- 0
	11-0-0 0
	01111- 0
	11-1-1 0
Add following truth table to pb_graph_pin 'lut6_out[0]'
	00--0- 0
	000--- 0
	-0--00 0
	-00--0 0
	101-11 0
	0--00- 0
	0-00-- 0
	11-0-0 0
	01111- 0
	11-1-1 0

Driver atom block: '25'
Pb atom blocks:'25', 
Input nets: A[1]  A[2]  B[1]  B[0]  B[2]  A[3]  
Output net: new_$abc$328$new_n27
Truth table before adaption to fracturable LUT'
	--0-0- 0
	-0---0 0
	----00 0
	000--- 0
	1-1--0 0
	-000-- 0
	011011 0
	-1-10- 0
	10111- 0
	1101-1 0
Add following truth table to pb_graph_pin 'lut6_out[0]'
	--0-0- 0
	-0---0 0
	----00 0
	000--- 0
	1-1--0 0
	-000-- 0
	011011 0
	-1-10- 0
	10111- 0
	1101-1 0

Driver atom block: '19'
Pb atom blocks:'19', 
Input nets: new_$abc$328$new_n25  new_$abc$328$new_n27  new_$abc$328$new_n26  new_$abc$328$new_n22  new_$abc$328$new_n23  new_$abc$328$new_n24  
Output net: Y[4]
Truth table before adaption to fracturable LUT'
	00100- 1
	01000- 1
	00011- 1
	01111- 1
	10010- 1
	11110- 1
	10001- 1
	11101- 1
	-00100 1
	-11100 1
	-00010 1
	-11010 1
	1000-0 1
	1110-0 1
	101110 1
	110110 1
	-01001 1
	-10001 1
	-00111 1
	-11111 1
	0010-1 1
	0100-1 1
	001-01 1
	010-01 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	00100- 1
	01000- 1
	00011- 1
	01111- 1
	10010- 1
	11110- 1
	10001- 1
	11101- 1
	-00100 1
	-11100 1
	-00010 1
	-11010 1
	1000-0 1
	1110-0 1
	101110 1
	110110 1
	-01001 1
	-10001 1
	-00111 1
	-11111 1
	0010-1 1
	0100-1 1
	001-01 1
	010-01 1

Driver atom block: '35'
Pb atom blocks:'35', 
Input nets: new_$abc$328$new_n23  new_$abc$328$new_n25  unconn  new_$abc$328$new_n22  new_$abc$328$new_n24  unconn  
Output net: Y[3]
Truth table before adaption to fracturable LUT'
	00-00- 1
	10-10- 1
	00-11- 1
	10-01- 1
	01-10- 1
	11-00- 1
	01-01- 1
	11-11- 1
Add following truth table to pb_graph_pin 'lut5_out[1]'
	00-000 1
	10-100 1
	00-110 1
	10-010 1
	01-100 1
	11-000 1
	01-010 1
	11-110 1

Driver atom block: '23'
Pb atom blocks:'23', 
Input nets: B[1]  B[2]  B[0]  A[2]  A[1]  A[3]  
Output net: new_$abc$328$new_n25
Truth table before adaption to fracturable LUT'
	01--10 1
	-1-010 1
	1--100 1
	10-1-0 1
	010-1- 1
	-1001- 1
	1-010- 1
	1001-- 1
	0-1-01 1
	001--1 1
	--1001 1
	-010-1 1
	111111 1
Add following truth table to pb_graph_pin 'lut6_out[0]'
	01--10 1
	-1-010 1
	1--100 1
	10-1-0 1
	010-1- 1
	-1001- 1
	1-010- 1
	1001-- 1
	0-1-01 1
	001--1 1
	--1001 1
	-010-1 1
	111111 1

Build truth tables for physical LUTs under clustered block 'out:Y[5]'...
Build truth tables for physical LUTs under clustered block 'out:Y[6]'...
Build truth tables for physical LUTs under clustered block 'out:Y[7]'...
Build truth tables for physical LUTs under clustered block 'out:Y[4]'...
Build truth tables for physical LUTs under clustered block 'out:Y[3]'...
Build truth tables for physical LUTs under clustered block 'out:Y[2]'...
Build truth tables for physical LUTs under clustered block 'out:Y[0]'...
Build truth tables for physical LUTs under clustered block 'out:Y[1]'...
Build truth tables for physical LUTs under clustered block 'A[0]'...
Build truth tables for physical LUTs under clustered block 'A[1]'...
Build truth tables for physical LUTs under clustered block 'A[2]'...
Build truth tables for physical LUTs under clustered block 'A[3]'...
Build truth tables for physical LUTs under clustered block 'B[0]'...
Build truth tables for physical LUTs under clustered block 'B[1]'...
Build truth tables for physical LUTs under clustered block 'B[2]'...
Build truth tables for physical LUTs under clustered block 'B[3]'...
Build truth tables for physical LUTs took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml

Confirm selected options when call command 'build_architecture_bitstream':
--write_file: fabric_indepenent_bitstream.xml
--read_file: off
--no_time_stamp: off
--verbose: off

Build fabric-independent bitstream for implementation 'mult4'

Generating bitstream for Switch blocks...Done
Generating bitstream for X-direction Connection blocks ...Done
Generating bitstream for Y-direction Connection blocks ...Done

Build fabric-independent bitstream for implementation 'mult4'
 took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Overwrite Bitstream


Overwrite Bitstream
 took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Warning 35: Directory path is empty and nothing will be created.
Write 8416 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
Write 8416 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.01 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Build non-fabric bitstream for implementation 'mult4'


Build non-fabric bitstream for implementation 'mult4'
 took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: build_fabric_bitstream

Confirm selected options when call command 'build_fabric_bitstream':
--verbose: off

Build fabric dependent bitstream


Build fabric dependent bitstream
 took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit --no_time_stamp

Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.bit
--format: plain_text
--filter_value: off
--path_only: off
--value_only: off
--trim_path: off
--fast_configuration: off
--keep_dont_care_bits: off
--wl_decremental_order: off
--no_time_stamp: on
--verbose: off
Warning 36: Directory path is empty and nothing will be created.
Write 8416 fabric bitstream into plain text file 'fabric_bitstream.bit'
Write 8416 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml --no_time_stamp

Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.xml
--format: xml
--filter_value: off
--path_only: off
--value_only: off
--trim_path: off
--fast_configuration: off
--keep_dont_care_bits: off
--wl_decremental_order: off
--no_time_stamp: on
--verbose: off
Warning 37: Directory path is empty and nothing will be created.
Write 8416 fabric bitstream into xml file 'fabric_bitstream.xml'
  Progress: 0%
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Write 8416 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_hierarchy --file ./fabric_hierarchy.txt

Confirm selected options when call command 'write_fabric_hierarchy':
--file, -f: ./fabric_hierarchy.txt
--module: off
--filter: off
--depth: off
--exclude_empty_modules: off
--verbose: off
Write fabric hierarchy to plain-text file './fabric_hierarchy.txt'
Outputted 1 modules as root
Write fabric hierarchy to plain-text file './fabric_hierarchy.txt' took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_io_info --file ./fabric_io_location.xml --verbose

Confirm selected options when call command 'write_fabric_io_info':
--file, -f: ./fabric_io_location.xml
--no_time_stamp: off
--verbose: on
Warning 38: Directory '.' already exists. Will overwrite contents
Write fabric I/O information to an XML file './fabric_io_location.xml'
Outputted 64 I/Os to XML file: ./fabric_io_location.xml
Write fabric I/O information to an XML file './fabric_io_location.xml' took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: write_fabric_verilog --file /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose  --default_net_type wire

Confirm selected options when call command 'write_fabric_verilog':
--file, -f: /home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC
--constant_undriven_inputs: off
--explicit_port_mapping: on
--include_timing: on
--print_user_defined_template: on
--default_net_type: wire
--no_time_stamp: off
--use_relative_path: off
--little_endian, -le: off
--verbose: on
Write Verilog netlists for FPGA fabric

Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC'
Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module'
Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb'
Succeed to create directory '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/routing'
Generating Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/inv_buf_passgate.v' for essential gates...Done
Writing Verilog netlist for configuration decoders '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/arch_encoder.v'...Done
Writing Verilog netlist for local decoders for multiplexers '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/local_encoder.v'...Done
Writing Verilog netlist for Multiplexer primitives '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/mux_primitives.v' ...Done
Writing Verilog netlist for Multiplexers '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/muxes.v' ...Done
Writing Verilog netlist for LUTs '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.v'...Done
Writing Verilog netlist for wires '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/wires.v'...Done
Writing Verilog netlist for memories '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/memories.v' ...Done
Writing Verilog netlist for shift register banks '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/shift_register_banks.v' ...Done
Creating template for user-defined Verilog modules '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_templates.v'...Done

Writing logical tiles...
Writing Verilog netlists for logic tile 'io' ...
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_io_mode_physical__iopad.v' for primitive pb_type 'iopad' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_io_mode_physical__iopad'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_io_mode_io_.v' for pb_type 'io' ...
Writing Verilog codes of pb_type 'logical_tile_io_mode_io_'...Done
Done

Writing Verilog netlists for logic tile 'clb' ...
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut6.v' for primitive pb_type 'frac_lut6' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut6'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v' for pb_type 'frac_logic' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v' for primitive pb_type 'ff' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v' for pb_type 'fabric' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_default__fle.v' for pb_type 'fle' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle'...Done
Writing Verilog netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/logical_tile_clb_mode_clb_.v' for pb_type 'clb' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_clb_'...Done
Done

Writing logical tiles...Done

Building physical tiles...
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_top.v' for physical tile 'io' at top side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_right.v' for physical tile 'io' at right side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_bottom.v' for physical tile 'io' at bottom side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_io_left.v' for physical tile 'io' at left side ...Done
Writing Verilog Netlist '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/lb/grid_clb.v' for physical_tile 'clb'...Done
Building physical tiles...Done

Writing Verilog netlist for top-level module of FPGA fabric '/home/moshida/OpenFPGA/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/mult4/MIN_ROUTE_CHAN_WIDTH/SRC/fpga_top.v'...Done
Written 74 Verilog modules in total
Write Verilog netlists for FPGA fabric
 took 0.02 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: write_full_testbench --file ./SRC --reference_benchmark_file_path mult4_output_verilog.v --explicit_port_mapping --bitstream fabric_bitstream.bit --simulator iverilog --default_net_type wire

Confirm selected options when call command 'write_full_testbench':
--file, -f: ./SRC
--dut_module: off
--bitstream: fabric_bitstream.bit
--simulator: iverilog
--fabric_netlist_file_path: off
--pin_constraints_file, -pcf: off
--bus_group_file, -bgf: off
--reference_benchmark_file_path: mult4_output_verilog.v
--fast_configuration: off
--explicit_port_mapping: on
--default_net_type: wire
--no_self_checking: off
--include_signal_init: off
--no_time_stamp: off
--use_relative_path: off
--little_endian, -le: off
--verbose: off
Write Verilog full testbenches for FPGA fabric

# Write autocheck testbench for FPGA top-level Verilog netlist for 'mult4'
Will use 8417 configuration clock cycles to top testbench
# Write autocheck testbench for FPGA top-level Verilog netlist for 'mult4' took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Write Verilog full testbenches for FPGA fabric
 took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: write_pnr_sdc --file ./SDC

Confirm selected options when call command 'write_pnr_sdc':
--file, -f: ./SDC
--flatten_names: off
--hierarchical: off
--output_hierarchy: off
--time_unit: off
--constrain_global_port: off
--constrain_non_clock_global_port: off
--constrain_grid: off
--constrain_sb: off
--constrain_cb: off
--constrain_configurable_memory_outputs: off
--constrain_routing_multiplexer_outputs: off
--constrain_switch_block_outputs: off
--constrain_zero_delay_paths: off
--no_time_stamp: off
--verbose: off
Succeed to create directory './SDC'
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc'
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc'
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc'
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.01 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc'
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Write SDC for constrain Switch Block timing for P&R flow
Write SDC for constrain Switch Block timing for P&R flow took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Write SDC for constrain Connection Block timing for P&R flow
Write SDC for constrain Connection Block timing for P&R flow took 0.00 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)
Write SDC for constraining grid timing for P&R flow
Write SDC for constraining grid timing for P&R flow took 0.01 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc

Confirm selected options when call command 'write_sdc_disable_timing_configure_ports':
--file, -f: ./SDC/disable_configure_ports.sdc
--flatten_names: off
--no_time_stamp: off
--verbose: off
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc'
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.01 seconds (max_rss 64.3 MiB, delta_rss +0.0 MiB)

Command line to execute: exit

Confirm selected options when call command 'exit':

Finish execution with 0 errors

The entire OpenFPGA flow took 0.171897 seconds

Thank you for using OpenFPGA!
Incr Slack updates 35 in 3.6619e-05 sec
Full Max Req/Worst Slack updates 7 in 4.382e-06 sec
Incr Max Req/Worst Slack updates 28 in 1.2421e-05 sec
Incr Criticality updates 19 in 3.7055e-05 sec
Full Criticality updates 16 in 2.8868e-05 sec
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