Merge pull request #20 from OFFTKP/addsl

assembler: Add XTheadBa support

README.md

@@ -32,6 +32,7 @@ Includes both 32-bit and 64-bit instructions in the following:
 | V             | 1.0     |
 | Ssctr         | 1.0 rc6 |
 | Sstc          | 0.5.4   |
+| XTheadBa      | 1.0     |
 | XTheadCondMov | 1.0     |
 | Zabha         | 1.0     |
 | Zacas         | 1.0     |

include/biscuit/assembler.hpp

@@ -331,6 +331,9 @@ class Assembler {
     void TH_MVEQZ(GPR rd, GPR value, GPR condition) noexcept;
     void TH_MVNEZ(GPR rd, GPR value, GPR condition) noexcept;
 
+    // XTheadBa Extension Instructions
+    void TH_ADDSL(GPR rd, GPR rs1, GPR rs2, uint32_t shift) noexcept;
+
     // Zicsr Extension Instructions
 
     void CSRRC(GPR rd, CSR csr, GPR rs) noexcept;

src/assembler.cpp

@@ -692,6 +692,13 @@ void Assembler::TH_MVNEZ(GPR rd, GPR value, GPR condition) noexcept {
     EmitRType(m_buffer, 0b0100001, condition, value, 0b001, rd, 0b0001011);
 }
 
+// XTheadBa Extension Instructions
+
+void Assembler::TH_ADDSL(GPR rd, GPR rs1, GPR rs2, uint32_t shift) noexcept {
+    BISCUIT_ASSERT(shift <= 3);
+    EmitRType(m_buffer, 0b0000000 | shift, rs2, rs1, 0b001, rd, 0b0001011);
+}
+
 // Zicsr Extension Instructions
 
 void Assembler::CSRRC(GPR rd, CSR csr, GPR rs) noexcept {

tests/src/assembler_xthead_tests.cpp

@@ -31,3 +31,26 @@ TEST_CASE("TH.MVNEZ", "[XThead]") {
     as.TH_MVNEZ(x1, x2, x3);
     REQUIRE(value == 0x4231108B);
 }
+
+TEST_CASE("TH.ADDSL", "[XThead]") {
+    uint32_t value = 0;
+    auto as = MakeAssembler64(value);
+
+    as.TH_ADDSL(x31, x30, x29, 0);
+    REQUIRE(value == 0x01DF1F8B);
+
+    as.RewindBuffer();
+
+    as.TH_ADDSL(x31, x30, x29, 1);
+    REQUIRE(value == 0x03DF1F8B);
+
+    as.RewindBuffer();
+
+    as.TH_ADDSL(x31, x30, x29, 2);
+    REQUIRE(value == 0x05DF1F8B);
+
+    as.RewindBuffer();
+
+    as.TH_ADDSL(x31, x30, x29, 3);
+    REQUIRE(value == 0x07DF1F8B);
+}