Release for version 3.14.0

Release notes:

• Added first version of interconnect generator (for HW designs)
  • For generating IP-XACT interconnect components and corresponding RTL automatically (RTL generation is experimental)
  • More info can be found in help pages
• Python scripts can be run on CLI startup with option -i
• Desired system view can be selected when opening a system design
• Changed save functions to be under a single button
• Enabled memory map header generator for IP-XACT 2022
• Improved bus interface editor
• Improved port map auto connector prefixes
• Improved the path searching algorithm
• Updated structured port validation and writing
• Enabled existing path search algorithms for memory map header generator
• Changes to ports and bus interfaces in component editor do not delete connections in HW design
• Fixes to expression parser
• Fixes to verilog, VHDL and memory map header generators
• Fixed VLNV editor crash in some situations
• Fixes to SW design editor
• Fixed documents containing the same components to not overwrite changes
• Fixed meta component parameter parsing
• Fixed Verilog importer port parsing
• Changed File naming in VHDL / Verilog generator
• Changed memory designer address range visualization when connection and item share ranges

Installer and Linux tar-package are available in SourceForge.

Release for version 3.13.5

Hotfix for 3.13.4

Release notes:

• Fixed bug introduced in 3.13.4 where rows couldn't be removed in some table editors
• Fixed VLNV editor crash and improved tab and shift+tab behaviour
• Fixed a crash when creating a register inside a register file inside another register file
• Changed default AUB for CPUs and address spaces to 8 bits

Installer and Linux tar-package are available in SourceForge.

Release for 3.13.4

Release notes:

• Reworked memory designer to correctly show memory connections
  • Designer now shows each address space as separate connection sets
  • Items can be displayed in multiple connections
  • Target-initiator path search now finds multiple paths instead of just the shortest
  • Simple view of the designer excludes connections that are out of bounds (of connected address space)
• Simplified file dependency scanning. File dependencies are no longer stored in IP-XACT files, except if manually created.
• Added option to toggle memory overlap on and off in memory designer
• Added ability to create IP-XACT 2022 components and designs through the Python API
• Fixed Verilog and VHDL dependency scanning. Only file set files are scanned for dependencies, other dependencies are marked as external.
• Fixed removal of multiple non-contiguous rows in tables
• Fixed writing tied value of ad-hoc port with direction out (Verilog generator)

Installer and Linux tar-package are available in SourceForge.

Release for 3.13.3

QoL improvements, bug fixes and parameter editors for bus and abstraction definitions.

Release notes:

• Document lock made optional. Can be changed in settings, locking is disabled by default.
• Added parameter editors to abstraction definition editor and bus definition editor, added expression support to port abstractions
• Added HW Designer tool shortcuts
• Added ability to open referenced bus and abstraction definitions in bus interfaces by right-clicking in the component editor tree
• Improved validation in the component editor
• Improved Windows installer
• Fixed launching Kactus2 in CLI mode on Windows
• Fixed design parameter dock window disappearing when switching tabs
• Fixed changes made in component editor not reflecting in edited design (bus interfaces, ports)
• Fixed issue with expression editors scrambling expression when overwriting current expression or a section of it
• Fixed parsing unary minuses in systemverilog expressions
• Fixed component mode condition validation
• Fixed various bugs leading to crashes

Installer and Linux tar-package are available in SourceForge.

Release for version 3.13.2

Improved HW designer, reworked memory designer, various bug fixes.

Installer and Linux tar-package are available in SourceForge.

See README at SourceForge for full list of updates.

Release for version 3.13.1

Fixes for issues regarding the 2022 IP-XACT standard.

Installer and Linux tar-package are available in SourceForge.

See README for full list of updates.

Release for version 3.13.0

Added IP-XACT 2022 standard support for existing Kactus2 workflows. It is now possible to create and edit IP-XACT components compliant with the new 2022 IP-XACT standard using Kactus2.

Installer and Linux tar-package are available in SourceForge.

See README for full list of updates.

Release for version 3.12.0

Markdown documentation generation, Renode platform generator plugin and visual update.

Installer and Linux tar-package are available in SourceForge.

See README for full list of updates.

Release for version 3.11.0

Technology update to Qt6

Installer and Linux tar-package are available in SourceForge.

See README for full list of updates.

Release for version 3.10.0

Python script improvements, crash fixes and subspace maps

Installer and Linux tar-package are available in SourceForge.

See README for full list of updates.