|
1 | 1 | =============================================================================== |
2 | 2 | RELEASE NOTES : Kactus2 |
3 | | - Copyright (c) 2012-2024 Tampere University |
| 3 | + Copyright (c) 2012-2025 Tampere University |
4 | 4 | https://research.tuni.fi/system-on-chip/tools |
5 | 5 | =============================================================================== |
6 | 6 | + Improvement or feature added |
7 | 7 | - Bug fix or something removed |
8 | 8 | * Changed or Information |
9 | 9 | =============================================================================== |
10 | 10 |
|
| 11 | +24/04/2024 3.13.4 |
| 12 | +---------------------------------------------------- |
| 13 | +* Reworked memory designer to correctly show memory connections |
| 14 | + * Designer now shows each address space as separate connection sets |
| 15 | + * Items can be displayed in multiple connections |
| 16 | + * Target-initiator path search now finds multiple paths instead of just the shortest |
| 17 | + * Simple view of the designer excludes connections that are out of bounds (of connected address space) |
| 18 | +* Simplified file dependency scanning. File dependencies are no longer stored in IP-XACT files, except if manually created. |
| 19 | ++ Added option to toggle memory overlap on and off in memory designer |
| 20 | ++ Added ability to create IP-XACT 2022 components and designs through the Python API |
| 21 | +- Fixed Verilog and VHDL dependency scanning. Only file set files are scanned for dependencies, other dependencies are marked as external. |
| 22 | +- Fixed removal of multiple non-contiguous rows in tables |
| 23 | +- Fixed writing tied value of ad-hoc port with direction out (Verilog generator) |
| 24 | + |
11 | 25 | 14/10/2024 3.13.3 |
12 | 26 | ---------------------------------------------------- |
13 | 27 | * Document lock made optional. Can be changed in settings, locking is disabled by default. |
|
0 commit comments