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Prevent 2d block loads with dimensions larger than the tensor block size #4088

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b090692
Prevent 2d block loads with dimensions larger than the tensor block size
alexbaden May 3, 2025
6ebc5b9
add lit test
alexbaden May 5, 2025
2bff578
Update test/TritonIntelGPU/blockptr_load.mlir
alexbaden May 5, 2025
37370e4
use mlir::ceil
alexbaden May 5, 2025
410e9ed
operate on num operands per 2D load pre assignment to outer/inner
alexbaden May 6, 2025
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18 changes: 18 additions & 0 deletions test/TritonIntelGPU/blockptr_load.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -273,6 +273,24 @@ module attributes {"ttg.num-warps" = 8 : i32, "ttg.threads-per-warp" = 16 : i32}

// -----

// COM: 2D block load reduced to be <= block size
// CHECK: llvm.func spir_funccc @_Z51intel_sub_group_2d_block_read_transform_8b_32r16x2cPU3AS1viiiDv2_iPj(!llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>, !llvm.ptr {llvm.nonnull, llvm.writeonly}) attributes {no_unwind, will_return}
#dpas = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 4, threadsPerWarp = 16, warpsPerCTA = [1, 4], repCluster = [1, 2], A = [8, 32], B = [32, 32], C = [8, 32]}>
#dot1 = #ttg.dot_op<{opIdx = 1, parent = #dpas, kWidth=4}>
module attributes {"ttg.num-warps" = 8 : i32, "ttg.threads-per-warp" = 16 : i32} {
tt.func public @matmul_no_scf_with_advance_kernel(%arg0: !tt.ptr<i8>, %arg1: !tt.ptr<i8>, %arg2: i64, %arg3: i64, %arg4: i64, %arg5: i64, %arg7: i64) {
%c0_i32 = arith.constant 0 : i32
%c1_i64 = arith.constant 1 : i64
%ptrB = tt.make_tensor_ptr %arg1, [%arg4, %arg3], [%arg7, %c1_i64], [%c0_i32, %c0_i32] {order = array<i32: 1, 0>} : <tensor<64x16xi8, #dot1>>
// CHECK-COUNT-1: llvm.call spir_funccc @_Z51intel_sub_group_2d_block_read_transform_8b_32r16x2cPU3AS1viiiDv2_iPj({{.*}}) {{.*}} : (!llvm.ptr<1>{{.*}}, i32, i32, i32, vector<2xi32>, !llvm.ptr{{.*}}) -> ()
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From the semantic of the type of <tensor<64x16xi8, #dot1>>, the elements of the N dim (The second dimension) is duplicated to the threads.

The triton-tensor-layout output information shows the value N and value N + 32 should be the same value.

[[   T0:0|  T0:32|  T16:0| T16:32|  T32:0| T32:32|  T48:0| T48:32, ...

But the lowering code seems fills the value with 0 by the block IO.

There will be flakey if the return value is not aligned to the semantic of the type.

The expected block IO shape seems should be 8b_32r16x1c, and use the return value to fill up the [32, 32] tile.

// CHECK-NOT: llvm.call spir_funccc @_Z51intel_sub_group_2d_block_read_transform_8b_32r16x2cPU3AS1viiiDv2_iPj({{.*}}) {{.*}} : (!llvm.ptr<1>{{.*}}, i32, i32, i32, vector<2xi32>, !llvm.ptr{{.*}}) -> ()
%B = tt.load %ptrB {boundaryCheck = array<i32: 0>, padding = 1 : i32, triton_intel_gpu.block_io = "row_major"} : !tt.ptr<tensor<64x16xi8, #dot1>>
tt.return
}
}

// -----

#dpas = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [1, 1], repCluster = [1, 2], A = [8, 16], B = [16, 32], C = [8, 32]}>
#dot_b = #ttg.dot_op<{opIdx = 1, parent = #dpas, kWidth = 2}>
module attributes {"ttg.num-warps" = 1 : i32, "ttg.threads-per-warp" = 16 : i32} {
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22 changes: 21 additions & 1 deletion third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp
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Expand Up @@ -1623,6 +1623,26 @@ struct LoadOpConversion
std::min(numOperandsPer2DloadN, 64 / totalBytesPerRowPerDPASOp);
vBlocks = numOperandsPer2DloadN;

// downscale if the load size is bigger than the block size
LLVM_DEBUG({
llvm::dbgs() << "numOperandsPer2DLoadM before downscaling = "
<< numOperandsPer2DLoadM << "\n";
llvm::dbgs() << "numOperandsPer2DloadN before downscaling = "
<< numOperandsPer2DloadN << "\n";
});

if (!isTransposeRequired) {
// transpose has specific requirements based on hardware limitations and
// optional flags
numOperandsPer2DLoadM =
std::min(numOperandsPer2DLoadM,
mlir::ceil<unsigned>(tensorShape[0], elemsPerDPASInst[0]));

numOperandsPer2DloadN =
std::min(numOperandsPer2DloadN,
mlir::ceil<unsigned>(tensorShape[1], elemsPerDPASInst[1]));
}

numOperandsOuterDimPerLoad =
isOperandA ? numOperandsPer2DLoadM : numOperandsPer2DloadN;
numOperandsInnerDimPerLoad =
Expand Down Expand Up @@ -1899,12 +1919,12 @@ struct LoadOpConversion
/*vnni_transform*/
(usePackedType && !isOperandA && !isTransposeRequired &&
originalElemBits != 32));
LLVM_DEBUG(llvm::dbgs() << "Generated load op: " << load2dOp << "\n");
if (failed(load2dOp.verify())) {
// Explicitly invoke verifier because `triton_gen` ops are
// immediately lowered further to a builtin call.
return failure();
}
LLVM_DEBUG(llvm::dbgs() << "Generated load op: " << load2dOp << "\n");

unsigned packedRowNum = opIdx == DpasEncodingAttr::OpIdx::OperandA
? numOperandsOuterDimPerLoad
Expand Down