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How to use Moore to covert VHDL?

Status: Open.

#253 In fabianschuiki/moore;

· HNULiMingyuan opened on Apr 10, 2024

Build fails due to type deduction

Status: Open.

#251 In fabianschuiki/moore;

· snarlawar123 opened on May 24, 2023

Build fails due to missing <code>Standard.h</code> file in mlir-c/Dialect

Status: Open.

#250 In fabianschuiki/moore;

· vani2620 opened on Feb 22, 2023

Desync between cargo build and repo.

Status: Open.

#248 In fabianschuiki/moore;

· samerogers opened on Aug 1, 2022

Failing to build on Mac

Status: Open.

#245 In fabianschuiki/moore;

· gussmith23 opened on Jul 12, 2022

Build and Install problems in moore

Status: Open.

#244 In fabianschuiki/moore;

· DeepFlyingSky opened on Apr 20, 2022

Is there a plan to support System Verilog features like Classes/Constraints/Interfaces?

Status: Open.

#239 In fabianschuiki/moore;

· jainamq opened on Mar 15, 2022

Eliminate HIR in favor of AST-specific queries

A-hirArea: High-level Intermediate Representation.Area: High-level Intermediate Representation.

L-vlogLanguage: Verilog and SystemVerilog.Language: Verilog and SystemVerilog.

Status: Open.

#237 In fabianschuiki/moore;

· fabianschuiki opened on Jan 21, 2022

Remove legacy LLHD crate codegen and dependency

A-codegenArea: Code generation.Area: Code generation.

A-depsArea: Dependencies.Area: Dependencies.

C-cleanupCategory: Clean up or refactor code.Category: Clean up or refactor code.

Status: Open.

#236 In fabianschuiki/moore;

· fabianschuiki opened on Nov 21, 2021

Add Moore MIR dialect and move codegen to CIRCT

A-codegenArea: Code generation.Area: Code generation.

C-enhancementCategory: Adding or improving on features.Category: Adding or improving on features.

L-vlogLanguage: Verilog and SystemVerilog.Language: Verilog and SystemVerilog.

P-highPriority: High.Priority: High.

Status: Open.

#235 In fabianschuiki/moore;

· fabianschuiki opened on Nov 21, 2021

problems about ports when build in hierachy

A-mirArea: Mid-level Intermediate Representation.Area: Mid-level Intermediate Representation.

C-bugCategory: This is a bug.Category: This is a bug.

L-vlogLanguage: Verilog and SystemVerilog.Language: Verilog and SystemVerilog.

P-highPriority: High.Priority: High.

Status: Open.

#231 In fabianschuiki/moore;

· Zhangyanting-1997 opened on Sep 8, 2021

Consider adding support for importing / exporting UHDM

C-enhancementCategory: Adding or improving on features.Category: Adding or improving on features.

Status: Open.

#229 In fabianschuiki/moore;

· mithro opened on Aug 17, 2021