Skip to content

problems about ports when build in hierachy #231

@Zhangyanting-1997

Description

@Zhangyanting-1997

When doing module instantiation, an error occurs when a port exists.
Netlist.zip
截屏2021-09-08 下午11 07 34

Metadata

Metadata

Assignees

No one assigned

    Labels

    A-mirArea: Mid-level Intermediate Representation.C-bugCategory: This is a bug.L-vlogLanguage: Verilog and SystemVerilog.P-highPriority: High.

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions