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18 followers · 1 following
  • Singapore
  • 23:33 (UTC +08:00)

Achievements

Achievement: Pair Extraordinairex3Achievement: Starstruckx2Achievement: YOLOAchievement: Pull Sharkx3Achievement: Quickdraw

Achievements

Achievement: Pair Extraordinairex3Achievement: Starstruckx2Achievement: YOLOAchievement: Pull Sharkx3Achievement: Quickdraw

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chuanseng-ng/README.md

💫 About Me:

  • 👀 I’m interested in tinkering in hardware and getting down dirty in software
  • Interests:
    • Python
    • TS/JS
    • HDL (SystemVerilog)
    • Digital Design & Verification (Directed/Assertion/UVM)


  • 🌱 I’m currently learning more about SystemVerilog & UVM/cocotb while working on personal Python projects
  • Ongoing Projects:
    • Claude AI assisted CPU + GPU-lite SoC design
    • HW digital design AI agent suite

🌐 Socials:

LinkedIn email

💻 Tech Stack:

Python TypeScript Verilog System Verilog

📊 GitHub Stats:



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  1. digital-chip-design-agents digital-chip-design-agents Public

    Digital HDL Design Full-stack Agents

    Python 140 36

  2. claude_verilog_test claude_verilog_test Public

    Test Claude AI's hardware design capabilities and expand own expertise in digital design

    Python 2 3

  3. BitBurner-Scripts BitBurner-Scripts Public

    Git repo to store all BitBurner scripts

    TypeScript

  4. TetraMem_SystolicArray2x2 TetraMem_SystolicArray2x2 Public

    SystemVerilog

  5. EE0040-Design-Automation-for-Camouflage-Circuits EE0040-Design-Automation-for-Camouflage-Circuits Public

    AY19/20 EEE FYP Logic Gate Camouflage & Attack Analysis

    Verilog