Feature: Nomenclature cleanup

src/target/adiv5_swd.c

@@ -87,7 +87,7 @@ static void dormant_to_swd_sequence(void)
 	swd_proc.seq_out(ADIV5_JTAG_TO_DORMANT_SEQUENCE1, 31U);
 	swd_proc.seq_out(ADIV5_JTAG_TO_DORMANT_SEQUENCE2, 8U);
 	/* Send the 128-bit Selection Alert sequence on SWDIOTMS */
-	DEBUG_INFO("Switching out of dormant state into SWD\n");
+	DEBUG_INFO("Switching from dormant to SWD\n");
 	swd_proc.seq_out(ADIV5_SELECTION_ALERT_SEQUENCE_0, 32U);
 	swd_proc.seq_out(ADIV5_SELECTION_ALERT_SEQUENCE_1, 32U);
 	swd_proc.seq_out(ADIV5_SELECTION_ALERT_SEQUENCE_2, 32U);

src/target/apollo3.c

@@ -1,8 +1,9 @@
 /*
  * This file is part of the Black Magic Debug project.
  *
- * Copyright (C) 2022-2023 1BitSquared <[email protected]>
+ * Copyright (C) 2022-2025 1BitSquared <[email protected]>
  * Written by Sid Price <[email protected]>
+ * Modified by Rachel Mant <[email protected]>
  *
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,9 +23,6 @@
 #include "target.h"
 #include "target_internal.h"
 
-static bool apollo_3_flash_erase(target_flash_s *flash, target_addr_t addr, size_t len);
-static bool apollo_3_flash_write(target_flash_s *flash, target_addr_t dest, const void *src, size_t len);
-
 #define APOLLO_3_FLASH_BASE_ADDRESS 0x00000000U
 #define APOLLO_3_FLASH_SIZE         0x00100000U
 #define APOLLO_3_FLASH_BLOCK_SIZE   0x2000U
@@ -81,6 +79,9 @@ static bool apollo_3_flash_write(target_flash_s *flash, target_addr_t dest, cons
 #define APOLLO_3_VENDOR_ID_ADDRESS 0x40020010U /* Vendor ID Register */
 #define APOLLO_3_VENDOR_ID         0x414d4251U
 
+static bool apollo_3_flash_erase(target_flash_s *flash, target_addr_t addr, size_t len);
+static bool apollo_3_flash_write(target_flash_s *flash, target_addr_t dest, const void *src, size_t len);
+
 static void apollo_3_add_flash(target_s *target)
 {
 	target_flash_s *flash = calloc(1, sizeof(*flash));
@@ -109,7 +110,7 @@ bool apollo_3_probe(target_s *target)
 	/* Read the CHIPPN register to gather MCU details */
 	uint32_t mcu_chip_partnum = target_mem32_read32(target, APOLLO_3_CHIPPN_REGISTER);
 	/* Check the chip is an Apollo 3 */
-	if ((mcu_chip_partnum & APOLLO_3_CHIPPN_PART_NUMBER_MASK) != 0x06000000) {
+	if ((mcu_chip_partnum & APOLLO_3_CHIPPN_PART_NUMBER_MASK) != 0x06000000U) {
 		DEBUG_INFO("Invalid chip type read\n");
 		return false;
 	}

src/target/at32f43x.c

@@ -1,8 +1,9 @@
 /*
  * This file is part of the Black Magic Debug project.
  *
- * Copyright (C) 2023-2024 1BitSquared <[email protected]>
+ * Copyright (C) 2023-2025 1BitSquared <[email protected]>
  * Written by ALTracer <[email protected]>
+ * Modified by Rachel Mant <[email protected]>
  *
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -37,21 +38,6 @@
 #include "cortexm.h"
 #include "stm32_common.h"
 
-static bool at32f43_cmd_option(target_s *target, int argc, const char **argv);
-static bool at32f43_cmd_uid(target_s *target, int argc, const char **argv);
-
-const command_s at32f43_cmd_list[] = {
-	{"option", at32f43_cmd_option, "Manipulate option bytes"},
-	{"uid", at32f43_cmd_uid, "Print unique device ID"},
-	{NULL, NULL, NULL},
-};
-
-static bool at32f43_flash_prepare(target_flash_s *flash);
-static bool at32f43_flash_erase(target_flash_s *flash, target_addr_t addr, size_t len);
-static bool at32f43_flash_write(target_flash_s *flash, target_addr_t dest, const void *src, size_t len);
-static bool at32f43_flash_done(target_flash_s *flash);
-static bool at32f43_mass_erase(target_s *target, platform_timeout_s *print_progess);
-
 /* Flash memory controller register map */
 #define AT32F43x_FLASH_REG_BASE   0x40023c00U
 #define AT32F43x_FLASH_UNLOCK     (AT32F43x_FLASH_REG_BASE + 0x04U)
@@ -134,6 +120,21 @@ static bool at32f43_mass_erase(target_s *target, platform_timeout_s *print_proge
 #define AT32F4x_PROJECT_ID 0x1ffff7f3U
 #define AT32F4x_FLASHSIZE  0x1ffff7e0U
 
+static bool at32f43_cmd_option(target_s *target, int argc, const char **argv);
+static bool at32f43_cmd_uid(target_s *target, int argc, const char **argv);
+
+const command_s at32f43_cmd_list[] = {
+	{"option", at32f43_cmd_option, "Manipulate option bytes"},
+	{"uid", at32f43_cmd_uid, "Print unique device ID"},
+	{NULL, NULL, NULL},
+};
+
+static bool at32f43_flash_prepare(target_flash_s *flash);
+static bool at32f43_flash_erase(target_flash_s *flash, target_addr_t addr, size_t len);
+static bool at32f43_flash_write(target_flash_s *flash, target_addr_t dest, const void *src, size_t len);
+static bool at32f43_flash_done(target_flash_s *flash);
+static bool at32f43_mass_erase(target_s *target, platform_timeout_s *print_progess);
+
 typedef struct at32f43_flash {
 	target_flash_s target_flash;
 	uint32_t bank_reg_offset; /* Flash register offset for this bank */
@@ -165,7 +166,7 @@ static void at32f43_add_flash(target_s *const target, const target_addr_t addr,
 	target_add_flash(target, target_flash);
 }
 
-static void at32f43_configure_dbgmcu(target_s *target)
+static void at32f43_configure_dbgmcu(target_s *const target)
 {
 	/*
 	 * Enable sleep state emulation (clocks fed by HICK)
@@ -184,7 +185,7 @@ static void at32f43_configure_dbgmcu(target_s *target)
 		target_mem32_write32(target, AT32F43x_DBGMCU_APB1_PAUSE, dbgmcu_apb1_pause | dbgmcu_apb1_pause_mask);
 }
 
-static bool at32f43_attach(target_s *target)
+static bool at32f43_attach(target_s *const target)
 {
 	if (!cortexm_attach(target))
 		return false;
@@ -193,7 +194,7 @@ static bool at32f43_attach(target_s *target)
 	return true;
 }
 
-static void at32f43_detach(target_s *target)
+static void at32f43_detach(target_s *const target)
 {
 	const uint32_t dbgmcu_ctrl = target_mem32_read32(target, AT32F43x_DBGMCU_CTRL);
 	const uint32_t dbgmcu_apb1_pause = target_mem32_read32(target, AT32F43x_DBGMCU_APB1_PAUSE);
@@ -205,7 +206,7 @@ static void at32f43_detach(target_s *target)
 }
 
 /* Identify AT32F43x "High Performance" line devices */
-static bool at32f43_detect(target_s *target, const uint16_t part_id)
+static bool at32f43_detect(target_s *const target, const uint16_t part_id)
 {
 	/*
 	 * AT32F435 EOPB0 ZW/NZW split reconfiguration unsupported,
@@ -304,7 +305,7 @@ static bool at32f43_detect(target_s *target, const uint16_t part_id)
 }
 
 /* Identify AT32F405 Mainstream devices */
-static bool at32f405_detect(target_s *target, const uint32_t series)
+static bool at32f405_detect(target_s *const target, const uint32_t series)
 {
 	/*
 	 * AT32F405/F402 always contain 1 bank with 128 sectors
@@ -335,7 +336,7 @@ static bool at32f405_detect(target_s *target, const uint32_t series)
 }
 
 /* Identify AT32F423 Value line devices */
-static bool at32f423_detect(target_s *target, const uint32_t series)
+static bool at32f423_detect(target_s *const target, const uint32_t series)
 {
 	/*
 	 * AT32F423 always has 48 KiB of SRAM and one of
@@ -363,7 +364,7 @@ static bool at32f423_detect(target_s *target, const uint32_t series)
 }
 
 /* Identify any Arterytek devices with Cortex-M4 and FPEC at 0x4002_3c00 */
-bool at32f43x_probe(target_s *target)
+bool at32f43x_probe(target_s *const target)
 {
 	// Artery clones use Cortex M4 cores
 	if ((target->cpuid & CORTEX_CPUID_PARTNO_MASK) != CORTEX_M4)
@@ -459,37 +460,30 @@ static bool at32f43_flash_busy_wait(
 	return !(status & AT32F43x_FLASH_STS_PRGMERR);
 }
 
-static bool at32f43_flash_prepare(target_flash_s *target_flash)
+static bool at32f43_flash_prepare(target_flash_s *const target_flash)
 {
 	target_s *target = target_flash->t;
 	const at32f43_flash_s *const flash = (at32f43_flash_s *)target_flash;
 	const uint32_t bank_reg_offset = flash->bank_reg_offset;
 	return at32f43_flash_unlock(target, bank_reg_offset);
 }
 
-static bool at32f43_flash_done(target_flash_s *target_flash)
+static bool at32f43_flash_done(target_flash_s *const target_flash)
 {
 	target_s *target = target_flash->t;
 	const at32f43_flash_s *const flash = (at32f43_flash_s *)target_flash;
 	const uint32_t bank_reg_offset = flash->bank_reg_offset;
 	return at32f43_flash_lock(target, bank_reg_offset);
 }
 
-static bool at32f43_flash_erase(target_flash_s *target_flash, target_addr_t addr, size_t len)
+static bool at32f43_flash_erase(target_flash_s *const target_flash, const target_addr_t addr, const size_t len)
 {
+	(void)len;
 	target_s *target = target_flash->t;
 	const at32f43_flash_s *const flash = (at32f43_flash_s *)target_flash;
 	const uint32_t bank_reg_offset = flash->bank_reg_offset;
 
-	if (len != target_flash->blocksize) {
-		DEBUG_ERROR(
-			"%s: Requested erase length %zu does not match blocksize %zu!\n", __func__, len, target_flash->blocksize);
-		return false;
-	}
-
 	at32f43_flash_clear_eop(target, bank_reg_offset);
-	DEBUG_TARGET("%s: 0x%08" PRIX32 "+%" PRIu32 " reg_base 0x%08" PRIX32 "\n", __func__, addr, (uint32_t)len,
-		bank_reg_offset + AT32F43x_FLASH_REG_BASE);
 
 	/* Prepare for page/sector erase */
 	target_mem32_write32(target, AT32F43x_FLASH_CTRL + bank_reg_offset, AT32F43x_FLASH_CTRL_SECERS);
@@ -503,16 +497,15 @@ static bool at32f43_flash_erase(target_flash_s *target_flash, target_addr_t addr
 	return at32f43_flash_busy_wait(target, bank_reg_offset, NULL);
 }
 
-static bool at32f43_flash_write(target_flash_s *target_flash, target_addr_t dest, const void *src, size_t len)
+static bool at32f43_flash_write(
+	target_flash_s *const target_flash, const target_addr_t dest, const void *src, const size_t len)
 {
 	target_s *target = target_flash->t;
 	const at32f43_flash_s *const flash = (at32f43_flash_s *)target_flash;
 	const uint32_t bank_reg_offset = flash->bank_reg_offset;
 	const align_e psize = ALIGN_32BIT;
 
 	at32f43_flash_clear_eop(target, bank_reg_offset);
-	DEBUG_TARGET("%s: 0x%08" PRIX32 "+%" PRIu32 " reg_base 0x%08" PRIX32 "\n", __func__, dest, (uint32_t)len,
-		bank_reg_offset + AT32F43x_FLASH_REG_BASE);
 
 	/* Write to bank corresponding to flash region */
 	target_mem32_write32(target, AT32F43x_FLASH_CTRL + bank_reg_offset, AT32F43x_FLASH_CTRL_FPRGM);
@@ -550,7 +543,7 @@ static bool at32f43_mass_erase(target_s *const target, platform_timeout_s *const
 	return true;
 }
 
-static bool at32f43_option_erase(target_s *target)
+static bool at32f43_option_erase(target_s *const target)
 {
 	/* bank_reg_offset is 0, option bytes belong to first bank */
 	at32f43_flash_clear_eop(target, 0);
@@ -654,7 +647,7 @@ static bool at32f43_option_write(target_s *const target, const uint32_t addr, co
 	return result;
 }
 
-static bool at32f43_cmd_option(target_s *target, int argc, const char **argv)
+static bool at32f43_cmd_option(target_s *const target, const int argc, const char **const argv)
 {
 	const uint32_t read_protected = target_mem32_read32(target, AT32F43x_FLASH_USD) & AT32F43x_FLASH_USD_RDP;
 	const bool erase_requested = argc == 2 && strcmp(argv[1], "erase") == 0;
@@ -712,7 +705,7 @@ static bool at32f43_cmd_option(target_s *target, int argc, const char **argv)
 	return true;
 }
 
-static bool at32f43_cmd_uid(target_s *target, int argc, const char **argv)
+static bool at32f43_cmd_uid(target_s *const target, const int argc, const char **const argv)
 {
 	(void)argc;
 	(void)argv;