This repository contains makefiles that can simplify the use of GNU make to drive the design and verification of FPGAs.
The following tools are supported at present:
| File Name | Tool | Application |
|---|---|---|
| vivado.mak | AMD/Xilinx Vivado | mixed language synthesis, implementation and simulation |
| vivado_post.mak | AMD/Xilinx Vivado | post-synthesis functional simulation |
| vitis.mak | AMD/Xilinx Vitis | MicroBlaze, MicroBlaze-V and ARM CPU software builds |
| vsim.mak | Siemens ModelSim/Questa | mixed language simulation |
| ghdl.mak | GHDL | VHDL simulation |
| nvc.mak | NVC | VHDL simulation |
Support for Intel/Altera Quartus Prime is planned.
Please note that the repository contains various other makefiles and scripts, in addition to the above - these are deprecated and will eventually disappear.