make_radiant.py

################################################################################
# make_radiant.py
# A part of make-fpga - see https://github.com/amb5l/make-fpga
# This script generates makefiles for use with GNU make to
# build FPGA designs with Lattice Radiant.
################################################################################

import sys,os,argparse
from make_fpga import *

# parse arguments

parser = argparse.ArgumentParser(
    prog='make_radiant.py',
    description='Create makefiles for building FPGA designs with Lattice Radiant',
   )
parser.add_argument(
    '--flow',
    choices=['cmd','ide'],
    help='tool flow (command line or IDE)',
    default='cmd'
   )
parser.add_argument(
    '--proj',
    help='project name',
    default='fpga'
   )
parser.add_argument(
    '--impl',
    help='implementation name',
    default='impl_1'
   )
parser.add_argument(
    '--arch',
    required=True,
    help='FPGA architecture e.g. ice40up'
   )
parser.add_argument(
    '--dev',
    required=True,
    help='FPGA device e.g. iCE40UP5K-SG48I'
   )
parser.add_argument(
    '--perf',
    help='FPGA performance grade e.g. High-Performance_1.2V',
   )
parser.add_argument(
    '--freq',
    help='FPGA frequency target for synthesis e.g. 25.0MHz'
   )
parser.add_argument(
    '--use_io_reg',
    choices=['Auto','True','False'],
    default='Auto',
    help='control I/O register packing'
   )
parser.add_argument(
    '--vhdl',
    choices=['1993','2008'],
    default='2008',
    help='enable VHDL-2008 support'
   )
parser.add_argument(
    '--work',
    help='work library (defaults to "work")',
    default='work'
   )
parser.add_argument(
    '--src',
    required=True,
    nargs='+',
    action='append',
    help='source(s) in compile order (append =LIB to specify library name)'
   )
parser.add_argument(
    '--ldc',
    nargs='+',
    action='append',
    help='logical (pre-synthesis) design constraints'
   )
parser.add_argument(
    '--pdc',
    nargs='+',
    action='append',
    help='physical (post-synthesis) design constraints'
   )
parser.add_argument(
    '--dep',
    nargs='+',
    action='append',
    help='other dependancies e.g. data files'
   )
parser.add_argument(
    '--top',
    required=True,
    help='top level design unit'
   )
parser.add_argument(
    '--gen',
    nargs='+',
    action='append',
    help='generic=value[,generic=value ...]'
   )

args=parser.parse_args()
c,d=process_src(args.src,args.work)
args.ldc=flatten(args.ldc)
args.pdc=flatten(args.pdc)
args.dep=flatten(args.dep)
args.gen=flatten(args.gen)

# output

print('# makefile generated by make_radiant.py (see https://github.com/amb5l/make-fpga)')
print('# for building an FPGA design using Lattice Radiant.')
print('# FLOW:', 'IDE (project mode)' if args.flow == 'ide' else 'command line (batch mode)')
print('')
print('.PHONY: all bin nvcm net ibis clean force')
print('all: bin')
print('force:')
print('')
print('################################################################################')
print('# design specific section')
print('')
if args.flow == 'ide':
    print('# project')
    print('PROJ:='+args.proj)
    print('IMPL:='+args.impl)
    print('')
print('# FPGA')
print('ARCH:='+args.arch)
print('DEV:='+args.dev)
print('PERF:='+(args.perf if args.perf else ''))
print('FREQ:='+(args.freq if args.freq else ''))
print('')
print('# sources in compilation order (source=library)')
print('VHDL:='+('2008' if args.vhdl else ''))
print('LIB:='+' '.join(d))
for l in d:
    print('SRC.%s:=%s' % (l,var_vals(d[l])))
print('SRC:='+' '.join(['$(SRC.%s)' % l for l in d]))
print('')
print('# logical (pre-synthesis) constraints')
print('LDC:='+var_vals(args.ldc))
print('')
print('# physical (post-synthesis) constraints')
print('PDC:='+var_vals(args.pdc))
print('')
print('# other synthesis prerequisites (e.g. data files)')
print('DEP:='+var_vals(args.dep))
print('')
print('# top level design unit')
print('TOP:='+args.top)
print('')
print('# top level VHDL generics / Verilog parameters')
print('GEN:='+var_vals(args.gen))
print('')
print('# use I/O registers option (Auto, True or False)')
print('USE_IO_REG:='+args.use_io_reg)
print('')
print('################################################################################')
print('# flow specific section')
print('')
if args.flow == 'ide':
    print('RDF:=$(PROJ).rdf')
    print('VM_SYN:=$(IMPL)/$(PROJ)_$(IMPL).vm')
    print('UDB_SYN:=$(IMPL)/$(PROJ)_$(IMPL)_syn.udb')
    print('UDB_MAP:=$(IMPL)/$(PROJ)_$(IMPL)_map.udb')
    print('UDB_PAR:=$(IMPL)/$(PROJ)_$(IMPL).udb')
    print('BIN:=$(IMPL)/$(PROJ)_$(IMPL).bin')
    print('NVCM:=$(IMPL)/$(PROJ)_$(IMPL).nvcm')
    print('NET:=$(IMPL)/$(PROJ)_$(IMPL)_vo.vo')
    print('SDF:=$(IMPL)/$(PROJ)_$(IMPL)_vo.sdf')
    print('IBIS:=$(IMPL)/IBIS/$(PROJ)_$(IMPL).ibs')
if args.flow == 'cmd':
    print('VM_SYN:=$(TOP)_syn.vm')
    print('UDB_SYN:=$(TOP)_syn.udb')
    print('UDB_MAP:=$(TOP)_map.udb')
    print('UDB_PAR:=$(TOP).udb')
    print('BIN:=$(TOP).bin')
    print('NVCM:=$(TOP).nvcm')
    print('NET:=$(TOP)_vo.vo')
    print('SDF:=$(TOP)_vo.sdf')
    print('IBIS:=IBIS/$(TOP).ibs')
print('')
print('bin: $(BIN)')
print('nvcm: $(NVCM)')
print('net: $(NET) $(SDF)')
print('ibis: $(IBIS)')
print('')
if args.flow == 'ide':
    print('comma:=,')
    print('space:=$(subst x, ,x)')
    print('')
    print('ifeq ($(OS),Windows_NT)')
    print('TCLSH:=pnmainc')
    print('else')
    print('TCLSH:=radiantc')
    print('endif')
    print('')
    print('TCLSHIM:=tclshim.tcl')
    print('$(TCLSHIM): force')
    print('\t@echo "puts [join \$$argv \\" \\"]; set e [catch {set r [eval [join \$$argv \\" \\"]]} m]; if \$$e {puts \$$m; exit \$$e} else {puts \$$r}" > $@')
    print('')
    print('TCLRUN:=$(TCLSH) $(TCLSHIM)')
    print('')
    print('# project recipe')
    print('RECIPE:=$(PROJ) $(DEV) $(IMPL) $(VHDL) $(SRC) $(LDC) $(PDC) $(TOP) $(GEN)')
    print('RECIPE_FILE:=$(PROJ).txt')
    print('$(RECIPE_FILE): force')
    print('\t@bash -c \'[ -f $@ ] && r=$$(< $@) || r=""; if [[ $$r != "$(RECIPE)" ]]; then echo "$(RECIPE)" > $@; rm -f $(RDF); fi\'')
    print('')
    print('# create project, set VHDL standard, add source, set generics, set top')
    print('$(RDF): $(RECIPE_FILE) $(SRC) $(LDC) $(PDC) | $(TCLSHIM)')
    print('\t@bash -c \'echo -e "\\033[0;32mCREATE PROJECT\\033[0m"\'')
    print('\tbash -c "$(TCLRUN) \\')
    print('\t\tprj_create \\')
    print('\t\t\t-name $(PROJ) \\')
    print('\t\t\t-dev $(DEV) \\')
    print('\t\t\t$(addprefix -performance ,$(PERF)) \\')
    print('\t\t\t-impl $(IMPL) \\')
    print('\t\t\t-synthesis LSE \';\' \\')
    print('\t\tprj_set_strategy_value -strategy Strategy1 PROP_LST_VHDL2008=$(if $(filter 2008,$(VHDL)),True,False) \';\' \\')
    print('\t\t$(foreach l,$(LIB), $(foreach s,$(SRC.$l), \\')
    print('\t\t prj_add_source -impl $(IMPL) -work $l -format $(if $(filter .vhd,$(suffix $s)),vhd,ver) $s \';\' \\')
    print('\t\t)) \\')
    print('\t\t$(foreach s,$(LDC) $(PDC), \\')
    print('\t\t prj_add_source -impl $(IMPL) $s \';\' \\')
    print('\t\t) \\')
    print('\t\tprj_set_impl_opt -impl $(IMPL) HDL_PARAM $(subst $(space),$(comma),$(GEN)) \';\' \\')
    print('\t\tprj_set_impl_opt -impl $(IMPL) top $(TOP) \';\' \\')
    print('\t\tprj_set_strategy_value -strategy Strategy1 lse_use_io_reg=$(USE_IO_REG) \';\' \\')
    print('\t\tprj_save \';\' \\')
    print('\t\tprj_close"')
    print('')
    print('# Synthesis (compile structural Verilog netlist from HDL source)')
    print('# and Post Synthesis (combine .vm and IP into Unified Database)')
    print('$(VM_SYN) $(UDB_SYN): $(SRC) $(LDC) $(PDC) $(DEP) | $(RDF)')
    print('\t@bash -c \'echo -e "\\033[0;32mSYNTHESIZE\\033[0m"\'')
    print('\tbash -c "$(TCLRUN) \\')
    print('\t\tprj_open $(RDF) \';\' \\')
    print('\t\tprj_run Synthesis -impl $(IMPL) \';\' \\')
    print('\t\tprj_save \';\' \\')
    print('\t\tprj_close"')
    print('')
    print('# Map (convert generic logic to device specific resources)')
    print('$(UDB_MAP): $(UDB_SYN)')
    print('\t@bash -c \'echo -e "\\033[0;32mMAP\\033[0m"\'')
    print('\tbash -c "$(TCLRUN) \\')
    print('\t\tprj_open $(RDF) \';\' \\')
    print('\t\tprj_run Map -impl $(IMPL) \';\' \\')
    print('\t\tprj_save \';\' \\')
    print('\t\tprj_close"')
    print('')
    print('# Place and Route')
    print('$(UDB_PAR): $(UDB_MAP)')
    print('\t@bash -c \'echo -e "\\033[0;32mPLACE AND ROUTE\\033[0m"\'')
    print('\tbash -c "$(TCLRUN) \\')
    print('\t\tprj_open $(RDF) \';\' \\')
    print('\t\tprj_run PAR -impl $(IMPL) \';\' \\')
    print('\t\tprj_save \';\' \\')
    print('\t\tprj_close"')
    print('')
    print('# Generate programming binary file')
    print('$(BIN): $(UDB_PAR)')
    print('\t@bash -c \'echo -e "\\033[0;32mGENERATE PROGRAMMING BINARY FILE\\033[0m"\'')
    print('\tbash -c "$(TCLRUN) \\')
    print('\t\tprj_open $(RDF) \';\' \\')
    print('\t\tprj_set_strategy_value -strategy Strategy1 bit_out_format=bin \';\' \\')
    print('\t\tprj_run Export -impl $(IMPL) -task Bitgen\';\' \\')
    print('\t\tprj_save \';\' \\')
    print('\t\tprj_close"')
    print('')
    print('# Generate NVCM programming file')
    print('$(NVCM): $(UDB_PAR)')
    print('\t@bash -c \'echo -e "\\033[0;32mGENERATE NVCM FILE\\033[0m"\'')
    print('\tbash -c "$(TCLRUN) \\')
    print('\t\tprj_open $(RDF) \';\' \\')
    print('\t\tprj_set_strategy_value -strategy Strategy1 bit_out_format=nvcm \';\' \\')
    print('\t\tprj_run Export -impl $(IMPL) -task Bitgen\';\' \\')
    print('\t\tprj_set_strategy_value -strategy Strategy1 bit_out_format=bin \';\' \\')
    print('\t\tprj_save \';\' \\')
    print('\t\tprj_close"')
    print('')
    print('# Generate Verilog netlist and structured delay file for timing simulation')
    print('$(NET) $(SDF): $(UDB_PAR)')
    print('\t@bash -c \'echo -e "\\033[0;32mGENERATE TIMING NETLIST AND DELAY FILE\\033[0m"\'')
    print('\tbash -c "$(TCLRUN) \\')
    print('\t\tprj_open $(RDF) \';\' \\')
    print('\t\tprj_run Export -impl $(IMPL) -task TimingSimFileVlg\';\' \\')
    print('\t\tprj_save \';\' \\')
    print('\t\tprj_close"')
    print('\t\t')
    print('# Generate IBIS model')
    print('$(IBIS): $(UDB_PAR)')
    print('\t@bash -c \'echo -e "\\033[0;32mGENERATE IBIS MODEL\\033[0m"\'')
    print('\tbash -c "$(TCLRUN) \\')
    print('\t\tprj_open $(RDF) \';\' \\')
    print('\t\tprj_run Export -impl $(IMPL) -task IBIS \';\' \\')
    print('\t\tprj_save \';\' \\')
    print('\t\tprj_close"')
    print('')
    print('clean:')
    print('\trm -f *.tcl *.txt *.rdf *.sty hdr_log .recovery .setting.ini')
    print('\trm -rf $(IMPL)')
if args.flow == 'cmd':
    print('')
    print('ifndef LATTICE_RADIANT')
    print('$(error LATTICE_RADIANT environment variable is not defined)')
    print('endif')
    print('')
    print('ifndef FOUNDRY')
    print('$(error Lattice FOUNDRY environment variable is not defined)')
    print('endif')
    print('')
    print('# Synthesis (compile structural Verilog netlist from HDL source)')
    print('$(VM_SYN): $(SRC) $(LDC) $(DEP)')
    print('\t@bash -c \'echo -e "\\033[0;32mSYNTHESIS\\033[0m"\'')
    print('\tsynthesis \\')
    print('\t\t-output_hdl $@ \\')
    print('\t\t-a $(ARCH) \\')
    print('\t\t-p $(word 1,$(subst -, ,$(DEV))) \\')
    print('\t\t-t $(shell echo $(DEV)| grep -Po "(?<=-)(.+\d+)") \\')
    print('\t\t$(addprefix -sp ,$(PERF)) \\')
    print('\t\t$(addprefix -frequency ,$(FREQ)) \\')
    print('\t\t$(addprefix -vh,$(VHDL)) \\')
    print('\t\t$(foreach l,$(LIB), $(foreach s,$(SRC.$l), \\')
    print('\t\t -lib $l -$(if $(filter .vhd,$(suffix $s)),vhd,ver) $s \\')
    print('\t\t)) \\')
    print('\t\t$(addprefix -sdc ,$(LDC)) \\')
    print('\t\t-use_io_reg $(if $(filter Auto,$(USE_IO_REG)),auto,$(if $(filter True,$(USE_IO_REG)),1,0)) \\')
    print('\t\t-top $(TOP) \\')
    print('\t\t$(subst =, ,$(addprefix -hdl_param ,$(GEN))) \\')
    print('\t\t-logfile $(basename $@).log')
    print('')
    print('# Post Synthesis (combine .vm and IP into Unified Database)')
    print('$(UDB_SYN): $(VM_SYN) $(LDC)')
    print('\t@bash -c \'echo -e "\\033[0;32mPOST SYNTHESIS\\033[0m"\'')
    print('\tpostsyn \\')
    print('\t\t-w \\')
    print('\t\t-a $(ARCH) \\')
    print('\t\t-p $(word 1,$(subst -, ,$(DEV))) \\')
    print('\t\t-t $(shell echo $(DEV)| grep -Po "(?<=-)(.+\d+)") \\')
    print('\t\t$(addprefix -sp ,$(PERF)) \\')
    print('\t\t$(addprefix -ldc ,$(LDC)) \\')
    print('\t\t-o $@ \\')
    print('\t\t-top \\')
    print('\t\t$(notdir $<)')
    print('')
    print('# Map (convert generic logic to device specific resources)')
    print('$(UDB_MAP): $(UDB_SYN) $(PDC)')
    print('\t@bash -c \'echo -e "\\033[0;32mMAP\\033[0m"\'')
    print('\tmap $^ -o $@ -mp $(basename $@).mrp -xref_sig -xref_sym')
    print('')
    print('# Place and Route')
    print('$(UDB_PAR): $(UDB_MAP) $(PDC)')
    print('\t@bash -c \'echo -e "\\033[0;32mPLACE AND ROUTE\\033[0m"\'')
    print('\tpar -w -n 1 -t 1 -stopzero $< $@')
    print('')
    print('# Generate programming binary file')
    print('$(BIN): $(UDB_PAR)')
    print('\t@bash -c \'echo -e "\\033[0;32mGENERATE PROGRAMMING BINARY FILE\\033[0m"\'')
    print('\tbitgen -w $< $@')
    print('')
    print('# Generate NVCM programming file')
    print('\t@bash -c \'echo -e "\\033[0;32mGENERATE NVCM FILE\\033[0m"\'')
    print('$(NVCM): $(UDB_PAR)')
    print('\tbitgen -d -w -nvcm -nvcmsecurity $< $@')
    print('')
    print('# Generate Verilog netlist and structured delay file for timing simulation')
    print('$(NET) $(SDF): $(UDB_PAR)')
    print('\t@bash -c \'echo -e "\\033[0;32mGENERATE TIMING NETLIST AND DELAY FILE\\033[0m"\'')
    print('\tbackanno -w -neg -x -o $(NET) -d $(SDF) $(addprefix -sp ,$(PERF)) $<')
    print('')
    print('# Generate IBIS model')
    print('$(IBIS): $(UDB_PAR)')
    print('\t@bash -c \'echo -e "\\033[0;32mGENERATE IBIS MODEL\\033[0m"\'')
    print('\tibisgen $< $(LATTICE_RADIANT)/cae_library/ibis/$(ARCH).ibs')
    print('')
    print('clean:')
    print('\trm -f *.udb *.par *.pad *.drc *.bgn *.bin *.nvcm *.vo *.sdf *_map.* *_postsyn.* *_synth.*')
    print('\trm -rf *.dir/ .vdbs/')