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@shtaxxx shtaxxx released this 07 Nov 08:23
· 1349 commits to master since this release
0.7.0
f965378

Update

This version includes some challenging updates of hardware interface abstractions.

  • veriloggen.types: Abstractions of frequent-appeared interfaces, such as on-chip memory and on-chip bus, are implemented. Please see the test codes in "tests/extension/types_/".
  • veriloggen.dataflow.DataflowManager is added: it manages dataflow variable implementations on an existing Module objects and automatically synthesizes native signal objects belonging to the Module.
  • veriloggen.dataflow supports read/write operations from outside of dataflow definitions.
  • veriloggen.FSM and Seq support more human-readable assignment definitions by the object call as a method. Please see the test codes in "tests/extension/fsm_/" and "tests/extension/seq_/".
  • The feature of existing Verilog importation has been improved.
  • Fundamental objects in veriloggen.core.types supports the bit_length() method to return its bit width.

Test environment

Mac OSX 10.11.6 (El Capitan)

  • python 3.5.2
  • python 2.7.12

Ubuntu 16.04 LTS

  • python 3.5.2
  • python 2.7.12
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