tests/tcg/ppc64: Add mffsce test

tests/tcg/ppc64/Makefile.target

@@ -11,6 +11,7 @@ endif
 $(PPC64_TESTS): CFLAGS += -mpower8-vector
 
 PPC64_TESTS += mtfsf
+PPC64_TESTS += mffsce
 
 ifneq ($(CROSS_CC_HAS_POWER10),)
 PPC64_TESTS += byte_reverse sha512-vector

tests/tcg/ppc64le/Makefile.target

@@ -24,6 +24,7 @@ run-sha512-vector: QEMU_OPTS+=-cpu POWER10
 run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10
 
 PPC64LE_TESTS += mtfsf
+PPC64LE_TESTS += mffsce
 PPC64LE_TESTS += signal_save_restore_xer
 PPC64LE_TESTS += xxspltw
 

tests/tcg/ppc64le/mffsce.c

@@ -0,0 +1,38 @@
+#include <stdlib.h>
+#include <stdint.h>
+#include <assert.h>
+
+#define MTFSF(FLM, FRB) asm volatile ("mtfsf %0, %1" :: "i" (FLM), "f" (FRB))
+#define MFFS(FRT) asm("mffs %0" : "=f" (FRT))
+#define MFFSCE(FRT) asm("mffsce %0" : "=f" (FRT))
+
+#define PPC_BIT_NR(nr) (63 - (nr))
+
+#define FP_VE (1ull << PPC_BIT_NR(56))
+#define FP_OE (1ull << PPC_BIT_NR(57))
+#define FP_UE (1ull << PPC_BIT_NR(58))
+#define FP_ZE (1ull << PPC_BIT_NR(59))
+#define FP_XE (1ull << PPC_BIT_NR(60))
+#define FP_NI (1ull << PPC_BIT_NR(61))
+#define FP_RN0 (1ull << PPC_BIT_NR(62))
+#define FP_RN1 (1ull << PPC_BIT_NR(63))
+
+int main(void)
+{
+    uint64_t frt, fpscr;
+    uint64_t last_8_bits = FP_VE | FP_UE | FP_ZE |
+                           FP_XE | FP_NI | FP_RN1;
+    MTFSF(0b11111111, last_8_bits); // set test value to cpu fpscr
+    MFFSCE(frt);
+    MFFS(fpscr);
+
+    // in the returned value
+    // should be as the cpu fpscr was before
+    assert((frt & 0xff) == last_8_bits);
+
+    // in the cpu fpscr
+    // last 3 bits should be unchanged and enable bits should be unset
+    assert((fpscr & 0xff) == (last_8_bits & 0x7));
+
+    return 0;
+}