Skip to content

A Personal hobby project to learn digital design and Verilog

Notifications You must be signed in to change notification settings

Nawras-Ahamed/100DaysOfRTL

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

100DaysOfRTL


DAY 1 : FULL ADDER

DAY 2 : FULL SUBTRACTOR

DAY 3 : 4X1 MUX

DAY 4 : 1X4 DMUX

DAY 5 : RIPPLE CARRY ADDER

DAY 6 : 8x1 MUX

DAY 7 : 1X8 DEMUX

DAY 8 : BCD ADDER

DAY 9 : RIPPLE CARRY ADDER/SUBTRACTOR

DAY 10 : CARRY LOOK AHEAD ADDER

DAY 11 : 8X3 ENCODER

DAY 12 : 3X8 DECODER

DAY 13 : PRORITY ENCODER


DAY 14 : 4 BIT BINARY TO GRAY CODE CONVERTER

DAY 15 : 4 BIT GRAY CODE TO BINARY CONVERTER

DAY 16 : 4 BIT BINARY TO XS-3 CODE CONVERTER

DAY 17 : 4 BIT BINARY TO BCD CONVERTER


DAY 18 : CLOCK GENERATOR

DAY 19 : ALU

DAY 20 : COMPARATOR


DAY 21 : SR LATCH

DAY 22 : SR FF (sync and async reset)

DAY 23 : D FF (sync and async reset)

DAY 24 : JK & T FF (sync and async reset)

DAY 25 : ASYNCHRONOUS UP COUNTER

DAY 26 : ASYNCHRONOUS DOWN COUNTER

DAY 27 : ASYNCHRONOUS UP/DOWN COUNTER

DAY 28 : EDGE DETECTOR

DAY 29 : MOD-N COUNTER

DAY 30 : ODD COUNTER

DAY 31 : PARITY GENERATOR

DAY 32 : RING AND JHONSON COUNTER

DAY 33 : GRAY COUNTER

DAY 34 : CLOCK FREQUENCY DIVIDER (N-BIT)


DAY 35 : SISO SHIFT REGISTER

DAY 36 : PISO SHIFT REGISTER

DAY 37 : SIPO SHIFT REGISTER

DAY 38 : PIPO SHIFT REGISTER

DAY 39 : UNIVERSAL SHIFT REGISTER

DAY 40 : BARREL SHIFTER

DAY 41 : LINEAR FEEDBACK SHIFT REGISTER

DAY 42 : RANDOM NUMBER GENERATOR USING LFSR

DAY 43 : ENDIANESS


DAY 44 : FSM-1 (BASIC ONE-HOT STYLE COUNTER)

DAY 45 : FSM-2 (MEALY FSM FOR RISING EDGE DETETCTION)

DAY 46 : FSM-3 (MOORE FSM FOR RISING EDGE DETETCTION)

DAY 47 : FSM-4 (MEALY FSM NON OVERLAPPING 1010 DETECTOR)

DAY 48 : FSM-4 (MEALY FSM OVERLAPPING 1010 DETECTOR)

DAY 49 : FSM-5 (SERIAL ADDER USING FSM/MOORE FSM)

DAY 50 : FSM-6 (SIMPLE VENDING MACHINE LOGIC)


DAY 51 : SINGLE PORT ROM

DAY 52 : SINGLE PORT RAM

DAY 53 : DUAL PORT RAM

DAY 54 : SYNCHRONOUS FIFO V1

DAY 55 : SYNCHRONOUS FIFO V2

DAY 56 : SYNCHRONOUS FIFO V3 (with almost_full , almost_empty flags)

DAY 57 : ASYNCHRONOUS FIFO


DAY 58 : FIXED PRIORITY ARBITER

DAY 59 : ROUND ROBIN ARBITER

DAY 60 : Variable Time Slice RR ARBITER


DAY 61 : PWM

DAY 62 : PWM with DUTY control


DAY 63 : Carry Skip Adder

DAY 64 : Carry Select Adder

DAY 65 : IEEE 754 Addition Subtraction

DAY 66 : IEEE 754 Multiplication

DAY 67 : IEEE 754 Division

DAY 68 : Pipelined Adder

DAY 69 : Wallace Tree Adder

DAY 70 : Radix-4 Booth Multiplier


DAY 71 : APB MASTER

DAY 72 : APB SLAVE


DAY 73 : SV - ENUM

DAY 74 : SV - ARRAYS

DAY 75 : SV - fork-join , wait-join

DAY 76 : SV - TB INTERFACES

DAY 78 : SV - TB RANDOM

DAY 79 : SV - TB CONSTRAINTS

DAY 80 : SV - TB QUEUES

DAY 81 : SV - TASKS & FUNCTIONS

DAY 82 : SV - MAILBOX FOR TB

DAY 83 : SV - EVENTS

DAY 84 : SV - TB FOR FULL ADDER

DAY 85 : SV - TB FOR ARITHMETIC AND LOGICAL UNIT

DAY 86 : SV - CLOCKING BLOCKS

DAY 87 : SV - ASSERTIONS

DAY 88 : SV - ASSERTIONS SEQUENCE

DAY 89 : SV - FUNCTIONAL COVERAGE - 1

DAY 90 : SV - FUNCTIONAL COVERAGE - 2


TOOLS AND SIMULATORS : ICARUS VERILOG 0.9.7 / YOSYS / GTKWAVE

About

A Personal hobby project to learn digital design and Verilog

Resources

Stars

Watchers

Forks