Merge branch 'valek-refactor-ll_pcie_freq' into 'devel'

refactor(amd_pcie_ip): set core clk frequency to 500 MHz for LL endpoint See merge request ndk/ndk-fpga!150
CESNET · Feb 12, 2025 · 787332b · 787332b
2 parents dc98ea6 + 5390b5d
commit 787332b
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diff --git a/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl b/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
@@ -61,6 +61,7 @@ if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} {
     set_property -dict [list \
         CONFIG.axisten_if_width {256_bit} \
         CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+        CONFIG.coreclk_freq {500} \
     ] $IP
 } else {
     # x16 properties

diff --git a/cards/amd/vcu118/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl b/cards/amd/vcu118/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
@@ -61,6 +61,7 @@ if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} {
     set_property -dict [list \
         CONFIG.axisten_if_width {256_bit} \
         CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+        CONFIG.coreclk_freq {500} \
     ] $IP
 } else {
     # x16 properties

diff --git a/cards/iwave/g35p/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl b/cards/iwave/g35p/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
@@ -65,6 +65,7 @@ if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} {
     set_property -dict [list \
         CONFIG.axisten_if_width {256_bit} \
         CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+        CONFIG.coreclk_freq {500} \
     ] $IP
 } else {
     # x16 properties

diff --git a/cards/silicom/fb2cghh/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl b/cards/silicom/fb2cghh/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
@@ -61,6 +61,7 @@ if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} {
     set_property -dict [list \
         CONFIG.axisten_if_width {256_bit} \
         CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+        CONFIG.coreclk_freq {500} \
     ] $IP
 } else {
     # x16 properties

diff --git a/cards/silicom/fb4cgg3/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl b/cards/silicom/fb4cgg3/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
@@ -61,6 +61,7 @@ if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} {
     set_property -dict [list \
         CONFIG.axisten_if_width {256_bit} \
         CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+        CONFIG.coreclk_freq {500} \
     ] $IP
 } else {
     # x16 properties