Merge branch 'cabal_dma_calypte_rtile' into 'devel'

Revise R-Tile PCIe and add Gen4 x16 mode

See merge request ndk/ndk-fpga!148

apps/minimal/build/a2700/app_conf.tcl

@@ -9,9 +9,17 @@
 # ------------------------------------------------------------------------------
 # DMA parameters:
 # ------------------------------------------------------------------------------
-# The minimum number of RX/TX DMA channels for this card is 32.
-set DMA_RX_CHANNELS      32
-set DMA_TX_CHANNELS      32
+
+if {$env(DMA_TYPE) == 4} {
+    # DMA Calypte not meet timing on R-Tile FPGAs with more than 16 channels.
+    set DMA_RX_CHANNELS 16
+    set DMA_TX_CHANNELS 16
+} else {
+    # 400G DMA Medusa requires at least 32 channels.
+    set DMA_RX_CHANNELS 32
+    set DMA_TX_CHANNELS 32
+}
+
 # In blocking mode, packets are dropped only when the RX DMA channel is off.
 # In non-blocking mode, packets are dropped whenever they cannot be sent.
 set DMA_RX_BLOCKING_MODE true

apps/minimal/build/agi-fh400g/app_conf.tcl

@@ -10,9 +10,17 @@
 # ------------------------------------------------------------------------------
 # DMA parameters:
 # ------------------------------------------------------------------------------
-# The minimum number of RX/TX DMA channels for this card is 32.
-set DMA_RX_CHANNELS      32
-set DMA_TX_CHANNELS      32
+
+if {$env(DMA_TYPE) == 4} {
+    # DMA Calypte not meet timing on R-Tile FPGAs with more than 16 channels.
+    set DMA_RX_CHANNELS 16
+    set DMA_TX_CHANNELS 16
+} else {
+    # 400G DMA Medusa requires at least 32 channels.
+    set DMA_RX_CHANNELS 32
+    set DMA_TX_CHANNELS 32
+}
+
 # In blocking mode, packets are dropped only when the RX DMA channel is off.
 # In non-blocking mode, packets are dropped whenever they cannot be sent.
 set DMA_RX_BLOCKING_MODE true

apps/minimal/build/ia-440i/app_conf.tcl

@@ -13,9 +13,17 @@
 # ------------------------------------------------------------------------------
 # DMA parameters:
 # ------------------------------------------------------------------------------
-# The minimum number of RX/TX DMA channels for this card is 16.
-set DMA_RX_CHANNELS      16
-set DMA_TX_CHANNELS      16
+
+if {$env(DMA_TYPE) == 4} {
+    # DMA Calypte not meet timing on R-Tile FPGAs with more than 16 channels.
+    set DMA_RX_CHANNELS 16
+    set DMA_TX_CHANNELS 16
+} else {
+    # 400G DMA Medusa requires at least 32 channels.
+    set DMA_RX_CHANNELS 32
+    set DMA_TX_CHANNELS 32
+}
+
 # In blocking mode, packets are dropped only when the RX DMA channel is off.
 # In non-blocking mode, packets are dropped whenever they cannot be sent.
 set DMA_RX_BLOCKING_MODE true

cards/bittware/ia-440i/config/card_conf.tcl

@@ -37,8 +37,9 @@ set EHIP_PORT_TYPE(0)  $env(EHIP_PORT_TYPE)
 # PCIe parameters (not all combinations work):
 # ------------------------------------------------------------------------------
 # Supported combinations for this card:
-# 1x PCIe Gen5 x16  -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: default configuration)
-# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1
+# 1x PCIe Gen4 x16  -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: for DMA Calypte)
+# 1x PCIe Gen5 x16  -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: for DMA Medusa)
+# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (Note: for DMA Medusa)
 # ------------------------------------------------------------------------------
 
 # Set default PCIe configuration

cards/bittware/ia-440i/config/card_const.tcl

@@ -32,12 +32,14 @@ set QSFP_I2C_ADDR(0) "0xA0"
 # Checking of parameter compatibility
 # ------------------------------------------------------------------------------
 
-if {!(($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 0) ||
+if {!(($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 0) ||
+      ($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 0) ||
       ($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1)) } {
     error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE!
 Allowed PCIe configurations:
-- 1xGen5x16  -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0
-- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1"
+- 1xGen4x16  -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (for DMA Calypte)
+- 1xGen5x16  -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (for DMA Medusa)
+- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (for DMA Medusa)"
 }
 
 # ------------------------------------------------------------------------------

cards/bittware/ia-440i/src/Modules.tcl

@@ -27,7 +27,7 @@ set ARCHGRP_ARR(IP_DEVICE_FAMILY) "Agilex"
 set ARCHGRP_ARR(IP_DEVICE)        $ARCHGRP_ARR(FPGA)
 
 set PCIE_CONF [dict create 0 "1x16" 1 "2x8"]
-set RTILE_PCIE_IP_NAME "rtile_pcie_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]"
+set RTILE_PCIE_IP_NAME "rtile_pcie_gen$ARCHGRP_ARR(PCIE_GEN)_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]"
 
 set ETH_CONF [dict create 400 "1x400g" ]
 # TODO: 200 "2x200g" 100 [expr {$ARCHGRP_ARR(ETH_PORT_CHAN,0) == 2 ? "2x100g" : "4x100g"}] 50 "8x50g" 40 "2x40g" 25 "8x25g" 10 "8x10g"

cards/bittware/ia-440i/src/Quartus.inc.tcl

@@ -17,6 +17,7 @@ source $CORE_BASE/Quartus.inc.tcl
 set CARD_ARCHGRP(CORE_BASE)          $CORE_BASE
 set CARD_ARCHGRP(IP_BUILD_DIR)       $CARD_BASE/src/ip
 set CARD_ARCHGRP(PCIE_ENDPOINT_MODE) $PCIE_ENDPOINT_MODE
+set CARD_ARCHGRP(PCIE_GEN)           $PCIE_GEN
 set CARD_ARCHGRP(NET_MOD_ARCH)       $NET_MOD_ARCH
 # Second dimension because of addition of an element of another array, just for clarity.
 set CARD_ARCHGRP(ETH_PORT_SPEED,0)   $ETH_PORT_SPEED(0)

cards/bittware/ia-440i/src/fpga.vhd

@@ -74,7 +74,7 @@ architecture FULL of FPGA is
     constant MISC_IN_WIDTH   : natural := 4;
     constant MISC_OUT_WIDTH  : natural := 4;
     constant ETH_LANES       : natural := 8;
-    constant DMA_ENDPOINTS   : natural := tsel(PCIE_ENDPOINT_MODE=1,PCIE_ENDPOINTS,2*PCIE_ENDPOINTS);
+    constant DMA_ENDPOINTS   : natural := tsel(DMA_TYPE=3, 4, 1); -- 400G DMA Medusa = 4x DMA_ENDPOINT
     constant STATUS_LEDS     : natural := 2; -- fake, this board has only 1 status LED
 
     signal status_led_g      : std_logic_vector(STATUS_LEDS-1 downto 0);

cards/bittware/ia-440i/src/ip/rtile_pcie.ip.tcl

@@ -1,90 +1,34 @@
+# rtile_pcie.ip.tcl: TCL script for generating R-Tile PCIe IP.
+# Copyright (C) 2025 CESNET z.s.p.o.
+# Author(s): Jakub Cabal <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
 package require -exact qsys 21.3
 
 array set PARAMS $IP_PARAMS_L
 source $PARAMS(IP_COMMON_TCL)
-
-proc do_adjust_rtile_pcie_ip_1x16 {} {
-}
-
-proc do_adjust_rtile_pcie_ip_2x8 {} {
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_0_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_1_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cap_slot_clk_config_hwtcl} {1}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_enable_cii_hwtcl} {1}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_address_width_user_hwtcl} {26}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_class_code_hwtcl} {131072}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_device_id_hwtcl} {0xc000}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_vendor_id_user_hwtcl} {6380}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_user_vsec_cap_enable_hwtcl} {1}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_virtual_pf0_user_vsec_offset_hwtcl} {3328}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {design_environment} {Unknown}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {standard_interface_selection_hwtcl} {0}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {top_topology_hwtcl} {Gen5 2x8, Interface - 512 bit}
-
-	set_interface_property p1_rx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st0
-	set_interface_property p1_rx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st_misc
-	set_interface_property p1_rx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st1
-	set_interface_property p1_tx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st_misc
-	set_interface_property p1_tx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st0
-	set_interface_property p1_tx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st1
-	set_interface_property p1_tx_ehp EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_ehp
-	set_interface_property p1_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_reset_status_n
-	set_interface_property p1_slow_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_slow_reset_status_n
-	set_interface_property p1_hip_status EXPORT_OF intel_rtile_pcie_ast_0.p1_hip_status
-	set_interface_property p1_power_mgnt EXPORT_OF intel_rtile_pcie_ast_0.p1_power_mgnt
-	set_interface_property p1_pld_gp EXPORT_OF intel_rtile_pcie_ast_0.p1_pld_gp
-	set_interface_property p1_cii EXPORT_OF intel_rtile_pcie_ast_0.p1_cii
-}
-
-# adjust parameters in "rtile_pcie_ip" system
-proc do_adjust_rtile_pcie_ip {device family ipname filename adjust_proc} {
-
-	load_system $filename
-	set_project_property DEVICE $device
-	set_project_property DEVICE_FAMILY $family
-	set_project_property HIDE_FROM_IP_CATALOG {true}
-
-	# common IP core parameters
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cap_slot_clk_config_hwtcl} {1}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_enable_cii_hwtcl} {1}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_address_width_user_hwtcl} {26}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_class_code_hwtcl} {131072}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_device_id_hwtcl} {0xc000}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_vendor_id_user_hwtcl} {6380}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_user_vsec_cap_enable_hwtcl} {1}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_virtual_pf0_user_vsec_offset_hwtcl} {3328}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {example_design_mode_hwtcl} {PIO/SRIOV}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {g5_pld_clkfreq_user_hwtcl} {400MHz}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {independent_perst_x16_hwtcl} {0}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {independent_warmcold_perst_hwtcl} {0}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {pipemode_sim_hwtcl} {0}
-	set_instance_parameter_value intel_rtile_pcie_ast_0 {true_independent_support_mode_user_hwtcl} {0}
-
-	# configuration-specific parameters
-	$adjust_proc
-
-	set_interface_property p0_cii EXPORT_OF intel_rtile_pcie_ast_0.p0_cii
-
-	save_system $ipname
-}
-
-proc do_nothing {} {}
-
-set cb do_nothing
-if {$PARAMS(PCIE_ENDPOINT_MODE) == 0} {
-	set cb do_adjust_rtile_pcie_ip_1x16
-} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 1} {
-	set cb do_adjust_rtile_pcie_ip_2x8
+source $PARAMS(IP_TEMPLATE_BASE)/pcie/rtile_pcie_conf_lib.tcl
+
+set PCI_VENDOR_ID 0x18EC
+set PCI_DEVICE_ID 0xC000
+set USR_CLKFREQ 400MHz
+
+load_system $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)]
+set_project_property DEVICE $PARAMS(IP_DEVICE)
+set_project_property DEVICE_FAMILY $PARAMS(IP_DEVICE_FAMILY)
+set_project_property HIDE_FROM_IP_CATALOG {true}
+
+# common IP core parameters
+do_rtile_pcie_common
+
+# configuration-specific parameters
+if {$PARAMS(PCIE_ENDPOINT_MODE) == 0 && $PARAMS(PCIE_GEN) == 4} {
+    do_rtile_pcie_gen4_1x16 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ
+} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 0 && $PARAMS(PCIE_GEN) == 5} {
+    do_rtile_pcie_gen5_1x16 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ
+} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 1 && $PARAMS(PCIE_GEN) == 5} {
+    do_rtile_pcie_gen5_2x8 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ
 }
 
-do_adjust_rtile_pcie_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] $cb
+save_system $PARAMS(IP_COMP_NAME)

cards/reflexces/agi-fh400g/config/card_conf.tcl

@@ -38,13 +38,13 @@ set EHIP_PORT_TYPE(0)  $env(EHIP_PORT_TYPE)
 # PCIe parameters (not all combinations work):
 # ------------------------------------------------------------------------------
 # Supported combinations for this card:
-# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1
-# 2x PCIe Gen4 x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1 (Note: default configuration)
-# 1x PCIe Gen4 x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (Note: limited DMA performance)
+# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (Note: for DMA Medusa only)
+# 2x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1 (Note: for DMA Medusa only)
+# 1x PCIe Gen4 x16  -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: for DMA Calypte only)
 # ------------------------------------------------------------------------------
 
 # Set default PCIe configuration
-set PCIE_CONF "2xGen4x8x8"
+set PCIE_CONF "2xGen5x8x8"
 if { [info exist env(PCIE_CONF)] } {
     set PCIE_CONF $env(PCIE_CONF)
 }

cards/reflexces/agi-fh400g/config/card_const.tcl

@@ -34,12 +34,14 @@ if { $BOARD_REV != 0 && $BOARD_REV != 1 && $BOARD_REV != 2} {
     error "Incompatible BOARD_REV value: $BOARD_REV"
 }
 
-if {!(($PCIE_ENDPOINTS == 4 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 1) ||
+if {!(($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 0) ||
+      ($PCIE_ENDPOINTS == 4 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1) ||
       ($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1) )} {
     error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE!
 Allowed PCIe configurations:
-- 2xGen4x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1
-- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1"
+- 2xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1 (for DMA Medusa only)
+- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (for DMA Medusa only)
+- 1xGen4x16  -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (for DMA Calypte only)"
 }
 
 # Enable/add PCIe Gen5 x16 for experiments only!

cards/reflexces/agi-fh400g/src/Modules.tcl

@@ -27,7 +27,7 @@ set ARCHGRP_ARR(IP_DEVICE_FAMILY) "Agilex"
 set ARCHGRP_ARR(IP_DEVICE)        $ARCHGRP_ARR(FPGA)
 
 set PCIE_CONF [dict create 0 "1x16" 1 "2x8"]
-set RTILE_PCIE_IP_NAME "rtile_pcie_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]"
+set RTILE_PCIE_IP_NAME "rtile_pcie_gen$ARCHGRP_ARR(PCIE_GEN)_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]"
 
 set ETH_CONF [dict create 400 "1x400g" 200 "2x200g" 100 [expr {$ARCHGRP_ARR(ETH_PORT_CHAN,0) == 2 ? "2x100g" : "4x100g"}] 50 "8x50g" 40 "2x40g" 25 "8x25g" 10 "8x10g"]
 set FTILE_ETH_IP_NAME "ftile_eth_[dict get $ETH_CONF $ARCHGRP_ARR(ETH_PORT_SPEED,0)]"

cards/reflexces/agi-fh400g/src/Quartus.inc.tcl

@@ -18,6 +18,7 @@ set CARD_ARCHGRP(CORE_BASE)          $CORE_BASE
 set CARD_ARCHGRP(IP_BUILD_DIR)       $CARD_BASE/src/ip
 set CARD_ARCHGRP(NET_MOD_ARCH)       $NET_MOD_ARCH
 set CARD_ARCHGRP(PCIE_ENDPOINT_MODE) $PCIE_ENDPOINT_MODE
+set CARD_ARCHGRP(PCIE_GEN)           $PCIE_GEN
 # Second dimension because of addition of an element of another array, just for clarity.
 set CARD_ARCHGRP(ETH_PORT_SPEED,0)   $ETH_PORT_SPEED(0)
 set CARD_ARCHGRP(ETH_PORT_CHAN,0)    $ETH_PORT_CHAN(0)

cards/reflexces/agi-fh400g/src/fpga.vhd

@@ -362,26 +362,13 @@ architecture FULL of FPGA is
     );
     end component emif_agi027_cal;
 
-    function f_dma_endpoints(PCIE_ENDPOINTS : natural; PCIE_EP_MODE : natural; PCIE_GEN : natural) return natural is
-        variable dma_ep_v : natural;
-    begin
-        dma_ep_v := PCIE_ENDPOINTS;
-        if (PCIE_EP_MODE = 0) then
-            dma_ep_v := 2*dma_ep_v;
-        end if;
-        if (PCIE_GEN = 5) then
-            dma_ep_v := 2*dma_ep_v;
-        end if;
-        return dma_ep_v;
-    end function;
-
     constant PCIE_LANES      : integer := 16;
     constant PCIE_CLKS       : integer := 2;
     constant PCIE_CONS       : integer := 2;
     constant MISC_IN_WIDTH   : integer := 64;
     constant MISC_OUT_WIDTH  : integer := 64 + 5;
     constant ETH_LANES       : integer := 8;
-    constant DMA_ENDPOINTS   : integer := f_dma_endpoints(PCIE_ENDPOINTS,PCIE_ENDPOINT_MODE,PCIE_GEN);
+    constant DMA_ENDPOINTS   : integer := tsel(DMA_TYPE=3, 4, 1); -- 400G DMA Medusa = 4x DMA_ENDPOINT
     constant USE_SODIMM_MEM  : boolean := not TEST_FW_PCIE1_ONBOARD_DDR4;
     constant MEM_PORTS       : integer := tsel(USE_SODIMM_MEM,2,1);
     constant MEM_ADDR_WIDTH  : integer := tsel(USE_SODIMM_MEM,29,26); --HPS:26, SODIMM:29;