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Merged
merged 10 commits into from
Jul 24, 2024
Merged

std.os.linux: A handful of random porting fixes, mostly for armeb and thumbeb #20719

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b3e82b8
std.os.linux: Import arch bits for armeb and thumbeb too.
alexrp Jul 21, 2024
b21de4d
std.os.linux: Define syscalls for armeb and thumbeb too.
alexrp Jul 21, 2024
fcbb192
std.os.linux: Define (MIN)SIGSTKSZ for all supported Linux architectu…
alexrp Jul 21, 2024
92bc802
std.os.linux: Also define MAP for armeb and thumbeb.
alexrp Jul 21, 2024
93311d6
std.os.linux: Also define O for armeb and thumbeb.
alexrp Jul 21, 2024
d2d325a
std.os.linux.AUDIT: Fix s390x; add loongarch64 and xtensa.
alexrp Jul 21, 2024
d694ddd
std.os.linux.tls: Set tls_variant correctly for thumbeb.
alexrp Jul 21, 2024
c631110
std.os.linux.tls: Set tls_tcb_size correctly for thumbeb.
alexrp Jul 21, 2024
0473457
std.os.linux.tls: Set some constants correctly for powerpcle.
alexrp Jul 21, 2024
2d4fc1b
std.os.linux.tls: Fix setThreadPointer() for armeb and thumbeb.
alexrp Jul 21, 2024
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81 changes: 72 additions & 9 deletions lib/std/os/linux.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ const arch_bits = switch (native_arch) {
.x86 => @import("linux/x86.zig"),
.x86_64 => @import("linux/x86_64.zig"),
.aarch64, .aarch64_be => @import("linux/arm64.zig"),
.arm, .thumb => @import("linux/arm-eabi.zig"),
.arm, .armeb, .thumb, .thumbeb => @import("linux/arm-eabi.zig"),
.riscv64 => @import("linux/riscv64.zig"),
.sparc64 => @import("linux/sparc64.zig"),
.mips, .mipsel => @import("linux/mips.zig"),
Expand Down Expand Up @@ -103,7 +103,7 @@ pub const SYS = switch (@import("builtin").cpu.arch) {
.x86 => syscalls.X86,
.x86_64 => syscalls.X64,
.aarch64, .aarch64_be => syscalls.Arm64,
.arm, .thumb => syscalls.Arm,
.arm, .armeb, .thumb, .thumbeb => syscalls.Arm,
.riscv64 => syscalls.RiscV64,
.sparc64 => syscalls.Sparc64,
.mips, .mipsel => syscalls.Mips,
Expand Down Expand Up @@ -142,7 +142,7 @@ pub const MAP = switch (native_arch) {
UNINITIALIZED: bool = false,
_: u5 = 0,
},
.aarch64, .aarch64_be, .arm, .thumb => packed struct(u32) {
.aarch64, .aarch64_be, .arm, .armeb, .thumb, .thumbeb => packed struct(u32) {
TYPE: MAP_TYPE,
FIXED: bool = false,
ANONYMOUS: bool = false,
Expand Down Expand Up @@ -290,7 +290,7 @@ pub const O = switch (native_arch) {
TMPFILE: bool = false,
_: u9 = 0,
},
.aarch64, .aarch64_be, .arm, .thumb => packed struct(u32) {
.aarch64, .aarch64_be, .arm, .armeb, .thumb, .thumbeb => packed struct(u32) {
ACCMODE: ACCMODE = .RDONLY,
_2: u4 = 0,
CREAT: bool = false,
Expand Down Expand Up @@ -4787,13 +4787,72 @@ pub fn CPU_COUNT(set: cpu_set_t) cpu_count_t {
}

pub const MINSIGSTKSZ = switch (native_arch) {
.x86, .x86_64, .arm, .mipsel => 2048,
.aarch64 => 5120,
.arc,
.arm,
.armeb,
.csky,
.hexagon,
.m68k,
.mips,
.mipsel,
.mips64,
.mips64el,
.powerpc,
.powerpcle,
.riscv32,
.riscv64,
.s390x,
.thumb,
.thumbeb,
.x86,
.x86_64,
.xtensa,
=> 2048,
.loongarch64,
.sparc,
.sparcel,
.sparc64,
=> 4096,
.aarch64,
.aarch64_be,
=> 5120,
.powerpc64,
.powerpc64le,
=> 8192,
else => @compileError("MINSIGSTKSZ not defined for this architecture"),
};
pub const SIGSTKSZ = switch (native_arch) {
.x86, .x86_64, .arm, .mipsel => 8192,
.aarch64 => 16384,
.arc,
.arm,
.armeb,
.csky,
.hexagon,
.m68k,
.mips,
.mipsel,
.mips64,
.mips64el,
.powerpc,
.powerpcle,
.riscv32,
.riscv64,
.s390x,
.thumb,
.thumbeb,
.x86,
.x86_64,
.xtensa,
=> 8192,
.aarch64,
.aarch64_be,
.loongarch64,
.sparc,
.sparcel,
.sparc64,
=> 16384,
.powerpc64,
.powerpc64le,
=> 32768,
else => @compileError("SIGSTKSZ not defined for this architecture"),
};

Expand Down Expand Up @@ -7294,7 +7353,7 @@ pub const AUDIT = struct {
ARMEB = toAudit(.armeb),
CSKY = toAudit(.csky),
HEXAGON = @intFromEnum(std.elf.EM.HEXAGON),
X86 = toAudit(.x86),
LOONGARCH64 = toAudit(.loongarch64),
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@alexrp alexrp Jul 22, 2024 •
edited
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Just noting that I plan to rewrite these audit bindings in a follow-up PR. There's no sense in doing std.Target.Cpu.Arch -> std.elf.EM here, especially since there is not a 1:1 mapping.

#20743

M68K = toAudit(.m68k),
MIPS = toAudit(.mips),
MIPSEL = toAudit(.mips) | LE,
Expand All @@ -7308,18 +7367,22 @@ pub const AUDIT = struct {
S390X = toAudit(.s390x),
SPARC = toAudit(.sparc),
SPARC64 = toAudit(.sparc64),
X86 = toAudit(.x86),
X86_64 = toAudit(.x86_64),
XTENSA = toAudit(.xtensa),

fn toAudit(arch: std.Target.Cpu.Arch) u32 {
var res: u32 = @intFromEnum(arch.toElfMachine());
if (arch.endian() == .little) res |= LE;
switch (arch) {
.aarch64,
.loongarch64,
.mips64,
.mips64el,
.powerpc64,
.powerpc64le,
.riscv64,
.s390x,
.sparc64,
.x86_64,
=> res |= @"64BIT",
Expand Down
28 changes: 22 additions & 6 deletions lib/std/os/linux/tls.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,23 @@ const TLSVariant = enum {
};

const tls_variant = switch (native_arch) {
.arm, .armeb, .thumb, .aarch64, .aarch64_be, .riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => TLSVariant.VariantI,
.arm,
.armeb,
.thumb,
.thumbeb,
.aarch64,
.aarch64_be,
.riscv32,
.riscv64,
.mips,
.mipsel,
.mips64,
.mips64el,
.powerpc,
.powerpcle,
.powerpc64,
.powerpc64le,
=> TLSVariant.VariantI,
.x86_64, .x86, .sparc64 => TLSVariant.VariantII,
else => @compileError("undefined tls_variant for this architecture"),
};
Expand All @@ -58,27 +74,27 @@ const tls_variant = switch (native_arch) {
const tls_tcb_size = switch (native_arch) {
// ARM EABI mandates enough space for two pointers: the first one points to
// the DTV while the second one is unspecified but reserved
.arm, .armeb, .thumb, .aarch64, .aarch64_be => 2 * @sizeOf(usize),
.arm, .armeb, .thumb, .thumbeb, .aarch64, .aarch64_be => 2 * @sizeOf(usize),
// One pointer-sized word that points either to the DTV or the TCB itself
else => @sizeOf(usize),
};

// Controls if the TP points to the end of the TCB instead of its beginning
const tls_tp_points_past_tcb = switch (native_arch) {
.riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => true,
.riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => true,
else => false,
};

// Some architectures add some offset to the tp and dtv addresses in order to
// make the generated code more efficient

const tls_tp_offset = switch (native_arch) {
.mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => 0x7000,
.mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => 0x7000,
else => 0,
};

const tls_dtv_offset = switch (native_arch) {
.mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => 0x8000,
.mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => 0x8000,
.riscv32, .riscv64 => 0x800,
else => 0,
};
Expand Down Expand Up @@ -150,7 +166,7 @@ pub fn setThreadPointer(addr: usize) void {
: [addr] "r" (addr),
);
},
.arm, .thumb => {
.arm, .armeb, .thumb, .thumbeb => {
const rc = @call(.always_inline, linux.syscall1, .{ .set_tls, addr });
assert(rc == 0);
},
Expand Down