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drivers: audio: sf32lb52x: audio codec driver #98701
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download code from github very very slow. the old PR is: |
| - uart | ||
| - gpio | ||
| - watchdog | ||
| - audio-codec |
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| - audio-codec | |
| - audio |
it should be used as a tag for some test/sample, otherwise has no utility.
https://docs.zephyrproject.org/latest/develop/test/twister.html#board-configuration
Speaking of which, this driver has to be tested (or at least built) in CI.
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fixed
gmarull
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Please make sure to not make unrelated changes into a big commit, split changes into chunks as needed. Also, make sure CI passes and do not open new PRs.
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Add more callback in DMA processing, Fix DMA size bug. Signed-off-by: Gang He <[email protected]>
Add audio codec device tree information for sf32lb52x.dtsi Signed-off-by: Gang He <[email protected]>
SF32LB52X audio HAL driver source code is not need in Zephyr driver. Signed-off-by: Gang He <[email protected]>
Support audio device that has both input and output function. Signed-off-by: Gang He <[email protected]>
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| # Copyright (c) 2025 Qingsong Gou <[email protected]> | |||
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why my name :)
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Fixed.
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| pll_calibration(cfg->reg); | ||
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| LOG_INF("%s done", __func__); |
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| LOG_INF("%s done", __func__); |
| struct sf32lb_audcodec_data *data = dev->data; | ||
| struct sf32lb_codec_hw_config *hw_cfg = &data->hw_config; | ||
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| memset(data, 0, sizeof(struct sf32lb_audcodec_data)); |
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| memset(data, 0, sizeof(struct sf32lb_audcodec_data)); |
| #include <zephyr/logging/log.h> | ||
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| #include <register.h> | ||
| #include <bf0_hal_pmu.h> |
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| #include <bf0_hal_pmu.h> |
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HAL_PMU_EnableAudio() need it, this func under $root_dir/module/hal/sifli
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check #100138 for pmu reigster access
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here is this PMU functuon under module/hal/sifli/
HAL_StatusTypeDef HAL_PMU_EnableAudio(int enable)
{
if (enable)
hwp_pmuc->HXT_CR1 |= PMUC_HXT_CR1_BUF_AUD_EN;
else
hwp_pmuc->HXT_CR1 &= (~PMUC_HXT_CR1_BUF_AUD_EN);
return HAL_OK;
}
move this function to this file and use sys_write32() ? this will access hwp_pmuc directly
it same that, it better to add audio clock in clock device tree and access PMUC_HXT_CR1_BUF_AUD_EN in clocl_control_sf32lb_rcc.c. codec driver only need to enable the clock by DT
| #include <register.h> | ||
| #include <bf0_hal_pmu.h> | ||
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| LOG_MODULE_REGISTER(siflicodec, CONFIG_AUDIO_CODEC_LOG_LEVEL); |
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| LOG_MODULE_REGISTER(siflicodec, CONFIG_AUDIO_CODEC_LOG_LEVEL); | |
| LOG_MODULE_REGISTER(sifli_codec, CONFIG_AUDIO_CODEC_LOG_LEVEL); |
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| static const struct device *codec_dev; | ||
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| static int config_dac_path(AUDCODEC_TypeDef *reg, uint16_t bypass) |
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change param coz register access is changed with upper comments
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AUDCODEC_TypeDef was defined in $root_dir/module/hal/sifli
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a previous version redefined a struct for all register, but it is recommended to use register.h,. so many registers for audio, unless redefined all register as dma_ sf32lb. c, which is prone to errors
| switch (channel) { | ||
| case 0: | ||
| reg->DAC_CH0_CFG = (1 << AUDCODEC_DAC_CH0_CFG_ENABLE_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_DOUT_MUTE_Pos) |
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using FIELD_PREP instead
| | (2 << AUDCODEC_DAC_CH0_CFG_DEM_MODE_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_DMA_EN_Pos) | ||
| | (6 << AUDCODEC_DAC_CH0_CFG_ROUGH_VOL_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_FINE_VOL_Pos) | ||
| | (1 << AUDCODEC_DAC_CH0_CFG_DATA_FORMAT_Pos) | ||
| | (dac_clk->sinc_gain << AUDCODEC_DAC_CH0_CFG_SINC_GAIN_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_DITHER_GAIN_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_DITHER_EN_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_CLK_ANA_POL_Pos); | ||
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| reg->DAC_CH0_CFG_EXT = (1 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_EN_Pos) | ||
| | (1 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_MODE_Pos) | ||
| | (1 << AUDCODEC_DAC_CH0_CFG_EXT_ZERO_ADJUST_EN_Pos) | ||
| | (2 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_INTERVAL_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_STAT_Pos); | ||
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| reg->DAC_CH0_DEBUG = (0 << AUDCODEC_DAC_CH0_DEBUG_BYPASS_Pos) | ||
| | (0xFF << AUDCODEC_DAC_CH0_DEBUG_DATA_OUT_Pos); | ||
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| break; | ||
| case 1: | ||
| reg->DAC_CH1_CFG = (1 << AUDCODEC_DAC_CH0_CFG_ENABLE_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_DOUT_MUTE_Pos) | ||
| | (2 << AUDCODEC_DAC_CH0_CFG_DEM_MODE_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_DMA_EN_Pos) | ||
| | (6 << AUDCODEC_DAC_CH0_CFG_ROUGH_VOL_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_FINE_VOL_Pos) | ||
| | (1 << AUDCODEC_DAC_CH0_CFG_DATA_FORMAT_Pos) | ||
| | (dac_clk->sinc_gain << AUDCODEC_DAC_CH0_CFG_SINC_GAIN_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_DITHER_GAIN_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_DITHER_EN_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_CLK_ANA_POL_Pos); | ||
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| reg->DAC_CH1_CFG_EXT = (1 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_EN_Pos) | ||
| | (1 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_MODE_Pos) | ||
| | (1 << AUDCODEC_DAC_CH0_CFG_EXT_ZERO_ADJUST_EN_Pos) | ||
| | (2 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_INTERVAL_Pos) | ||
| | (0 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_STAT_Pos); | ||
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| reg->DAC_CH1_DEBUG = (0 << AUDCODEC_DAC_CH0_DEBUG_BYPASS_Pos) | ||
| | (0xFF << AUDCODEC_DAC_CH0_DEBUG_DATA_OUT_Pos); |
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same, using FIELD_PREP instead
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these was ported from other platform, careful and meticulous modifications are required
| } else { | ||
| LOG_ERR("dma err"); | ||
| } | ||
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empty line, run clang format
| static struct sf32lb_audcodec_data data##n = { \ | ||
| }; \ |
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| static struct sf32lb_audcodec_data data##n = { \ | |
| }; \ | |
| static struct sf32lb_audcodec_data data##n; \ |
audio playback and capure, extend API in codec.h Signed-off-by: ljq-ctrl <[email protected]>
Add audio codec in board device tree, including PA control pin. Signed-off-by: Gang He <[email protected]>
Add audio loop back sample Signed-off-by: ljq-ctrl <[email protected]>
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| .. zephyr:code-sample:: codec | |||
| :name: codec | |||
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| :name: codec | |
| :name: audio codec |
| sample: | ||
| description: onchip audio codec example | ||
| application | ||
| name: codec |
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| name: codec | |
| name: audio codec |



…m #97906
audio playback and capure, extend API in codec.h