drivers: eth: microchip: Introduce G1 Ethernet Driver

boards/microchip/sam/sam_e54_xpro/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING

boards/microchip/sam/sam_e54_xpro/sam_e54_xpro-pinctrl.dtsi

@@ -19,4 +19,22 @@
 			pinmux = <PC18F_TCC0_WO2>;
 		};
 	};
+	gmac_rmii: gmac_rmii {
+		group1 {
+			pinmux = <PA14L_GMAC_GTXCK>,
+				 <PA17L_GMAC_GTXEN>,
+				 <PA18L_GMAC_GTX0>,
+				 <PA19L_GMAC_GTX1>,
+				 <PC20L_GMAC_GRXDV>,
+				 <PA13L_GMAC_GRX0>,
+				 <PA12L_GMAC_GRX1>,
+				 <PA15L_GMAC_GRXER>;
+		};
+	};
+	mdio_default: mdio_default {
+		group1 {
+			pinmux = <PC11L_GMAC_GMDC>,
+				 <PC12L_GMAC_GMDIO>;
+		};
+	};
 };

boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.dts

@@ -192,10 +192,34 @@
 	channels = <6>;
 };
 
+&gmac {
+	status = "okay";
+	compatible = "microchip,gmac-g1-eth";
+
+	pinctrl-0 = <&gmac_rmii>;
+	pinctrl-names = "default";
+
+	phy-handle = <&phy>;
+};
+
+&mdio {
+	status = "okay";
+	compatible = "microchip,gmac-g1-mdio";
+
+	pinctrl-0 = <&mdio_default>;
+	pinctrl-names = "default";
+
+	phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		status = "okay";
+		reg = <0>;
+	};
+};
+
 &portb {
 	status = "okay";
 };
 
 &portc {
 	status = "okay";
-};
+};

boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.yaml

@@ -19,4 +19,5 @@ supported:
   - reset
   - shell
   - uart
+  - netif:eth
 vendor: microchip

drivers/ethernet/CMakeLists.txt

@@ -30,6 +30,7 @@ zephyr_library_sources_ifdef(CONFIG_ETH_LITEX_LITEETH	eth_litex_liteeth.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_SMSC911X	eth_smsc911x.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_STELLARIS	eth_stellaris.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_W5500		eth_w5500.c)
+zephyr_library_sources_ifdef(CONFIG_ETH_MCHP_GMAC_G1	eth_mchp_gmac_g1.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_SAM_GMAC	eth_sam_gmac.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_CYCLONEV	eth_cyclonev.c)
 zephyr_library_sources_ifdef(CONFIG_SLIP_TAP		eth_slip_tap.c)

drivers/ethernet/Kconfig

@@ -54,6 +54,7 @@ source "drivers/ethernet/Kconfig.enc424j600"
 source "drivers/ethernet/Kconfig.esp32"
 source "drivers/ethernet/Kconfig.e1000"
 source "drivers/ethernet/Kconfig.sam_gmac"
+source "drivers/ethernet/Kconfig.mchp"
 source "drivers/ethernet/Kconfig.stm32_hal"
 source "drivers/ethernet/Kconfig.dwmac"
 source "drivers/ethernet/Kconfig.smsc911x"

drivers/ethernet/Kconfig.mchp

@@ -0,0 +1,129 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config ETH_MCHP_GMAC_G1
+	bool "Microchip Ethernet driver"
+	default y
+	depends on NET_BUF_FIXED_DATA_SIZE
+	depends on DT_HAS_MICROCHIP_GMAC_G1_ETH_ENABLED
+	select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
+	select MDIO
+	select ETH_DSA_SUPPORT
+	select PINCTRL
+	help
+	  Enable Microchip MCU Family Ethernet driver.
+
+# Define menu symbol for configuring ethernet features
+menuconfig ETH_MCHP_GMAC
+	bool "Microchip GMAC Ethernet driver"
+	default y
+	depends on ETH_MCHP_GMAC_G1
+	help
+	  Enable support for Microchip clock controller driver.
+
+if ETH_MCHP_GMAC
+
+# Workaround for not being able to have commas in macro arguments
+DT_ETH_MCHP_PATH := $(dt_nodelabel_path,gmac)
+
+# Just for readability, to keep the following lines shorter.
+DT_ETH_MCHP_NQ := $(dt_node_int_prop_int,$(DT_ETH_MCHP_PATH),num-queues)
+
+config ETH_MCHP_QUEUES
+	int "Number of active hardware TX and RX queues"
+	default 1
+	range 1 $(DT_ETH_MCHP_NQ) if SOC_SERIES_SAME70 || \
+						SOC_SERIES_SAMV71 || \
+						SOC_SERIES_SAM4E || \
+						SOC_SERIES_SAME54
+	help
+	  Select the number of hardware queues used by the driver. Packets will be
+	  routed to appropriate queues based on their priority.
+
+config ETH_MCHP_FORCE_QUEUE
+	bool "Force all traffic to be routed through a specific queue"
+	depends on ETH_MCHP_QUEUES > 1
+	depends on NET_TC_RX_COUNT < 5
+	help
+	  This option is meant to be used only for debugging. Use it to force all
+	  traffic to be routed through a specific hardware queue. With this enabled
+	  it is easier to verify whether the chosen hardware queue actually works.
+	  This works only if there are four or fewer RX traffic classes enabled, as
+	  the SAM GMAC hardware supports screening up to four traffic classes.
+
+config ETH_MCHP_FORCED_QUEUE
+	int "Queue to force the packets to"
+	depends on ETH_MCHP_FORCE_QUEUE
+	default 0
+	range 0 1 if ETH_MCHP_QUEUES = 2
+	range 0 2 if ETH_MCHP_QUEUES = 3
+	range 0 3 if ETH_MCHP_QUEUES = 4
+	range 0 4 if ETH_MCHP_QUEUES = 5
+	range 0 5 if ETH_MCHP_QUEUES = 6
+	help
+	  Which queue to force the routing to. This affects both the TX and RX queues
+	  setup.
+
+config ETH_MCHP_BUF_RX_COUNT
+	int "Network RX buffers preallocated by the SAM ETH driver"
+	default 12
+	help
+	  Number of network buffers that will be permanently allocated by the
+	  Ethernet driver. These buffers are used in receive path. They are
+	  preallocated by the driver and made available to the GMAC module to be
+	  filled in with incoming data. Their number has to be large enough to fit
+	  at least one complete Ethernet frame. SAM ETH driver will always allocate
+	  that amount of buffers for itself thus reducing the NET_BUF_RX_COUNT
+	  which is a total amount of RX data buffers used by the whole networking
+	  stack. One has to ensure that NET_PKT_RX_COUNT is large enough to
+	  fit at least two Ethernet frames: one being received by the GMAC module
+	  and the other being processed by the higher layer networking stack.
+
+config ETH_MCHP_MAC_I2C_EEPROM
+	default y
+	select I2C
+	bool "Read from an I2C EEPROM"
+	help
+	  Read MAC address from an I2C EEPROM.
+
+if ETH_MCHP_MAC_I2C_EEPROM
+
+config ETH_MCHP_MAC_I2C_INT_ADDRESS
+	hex "I2C EEPROM internal address"
+	default 0x9A
+	range 0 0xffffffff
+	help
+	  Internal address of the EEPROM chip where the MAC address is stored.
+	  Chips with 1 to 4 byte internal address size are supported. Address
+	  size has to be configured in a separate Kconfig option.
+
+config ETH_MCHP_MAC_I2C_INT_ADDRESS_SIZE
+	int "I2C EEPROM internal address size"
+	default 1
+	range 1 4
+	help
+	  Size (in bytes) of the internal EEPROM address.
+
+endif # ETH_MCHP_MAC_I2C_EEPROM
+
+config PTP_CLOCK_SAM_GMAC
+	bool "SAM GMAC PTP clock driver support"
+	default y
+	depends on PTP_CLOCK
+	help
+	  Enable SAM GMAC PTP Clock support.
+
+config ETH_MCHP_RX_THREAD_STACK_SIZE
+	int "MCHP RX Work thread stack size"
+	default 1600
+	help
+	  RX thread stack size in bytes.
+
+config ETH_MCHP_RX_THREAD_PRIORITY
+	int "MCHP RX work thread priority"
+	default 2
+	help
+	  Ethernet Driver handles RX in workqueue thread.
+	  This options sets the priority of that thread.
+
+endif # ETH_MCHP_GMAC