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arch: riscv: use riscv Kconfigs to set 64BIT and CPU_HAS_FPU #97981

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Merged
merged 2 commits into from
Oct 24, 2025
Merged

arch: riscv: use riscv Kconfigs to set 64BIT and CPU_HAS_FPU #97981

merged 2 commits into from
Oct 24, 2025

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  • use RISCV_ISA_RV64I to set 64BIT
  • use RISCV_ISA_EXT_F to set CPU_HAS_FPU
  • use RISCV_ISA_EXT_D to set CPU_HAS_FPU_DOUBLE_PRECISION

@maass-hamburg maass-hamburg marked this pull request as ready for review October 21, 2025 09:56
@maass-hamburg maass-hamburg mentioned this pull request Oct 22, 2025
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@maass-hamburg
arch: riscv: use RISCV_ISA_RV64I to set 64BIT
dfe203f 
use CONFIG_RISCV_ISA_RV64I to set CONFIG_64BIT.

Signed-off-by: Fin Maaß <[email protected]>
@maass-hamburg
arch: riscv: use RISCV_ISA_EXT_F to set CPU_HAS_FPU
e2870d0 
use CONFIG_RISCV_ISA_EXT_F to set CONFIG_CPU_HAS_FPU.
Same for CONFIG_RISCV_ISA_EXT_D and
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION.

Signed-off-by: Fin Maaß <[email protected]>
@sonarqubecloud
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Quality Gate Passed Quality Gate passed

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0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

@maass-hamburg maass-hamburg added this to the v4.3.0 milestone Oct 23, 2025
@cfriedt cfriedt merged commit 24669df into zephyrproject-rtos:main Oct 24, 2025
30 of 33 checks passed
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Reviewers

@nashif nashif nashif approved these changes

@fkokosinski fkokosinski fkokosinski approved these changes

@Dino-Li Dino-Li Awaiting requested review from Dino-Li

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@kgugala kgugala

@tgorochowik tgorochowik

@fkokosinski fkokosinski

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area: Boards/SoCs area: RISCV RISCV Architecture (32-bit & 64-bit) platform: Andes Technology platform: Bouffalo Lab platform: ITE ITE

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v4.3.0

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7 participants

@maass-hamburg @nashif @fkokosinski @cfriedt @kgugala @tgorochowik @zephyrbot