dts: arm: xilinx: zynq7000: add i2c0 and i2c1 controller nodes #90071
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Add device tree nodes for the Cadence I2C controllers present in Zynq-7000 SoCs. These I2C controllers are implemented as hard IP blocks in the Processing System (PS) portion of the chip. They are located at 0xe0004000 (i2c0) and 0xe0005000 (i2c1), respectively. Each node includes standard properties such as compatible strings, memory-mapped address ranges, interrupt configuration, and FIFO depth. Both nodes are marked as "disabled" by default and can be enabled in board-specific overlays depending on application needs. Reference: UG585 Zynq-7000 SoC TRM Link: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM Signed-off-by: Hank Wang <[email protected]>
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Add device tree nodes for the Cadence I2C controllers present in Zynq-7000 SoCs. These I2C controllers are implemented as hard IP blocks in the Processing System (PS) portion of the chip. They are located at 0xe0004000 (i2c0) and 0xe0005000 (i2c1), respectively.
Each node includes standard properties such as compatible strings, memory-mapped address ranges, interrupt configuration, and FIFO depth. Both nodes are marked as "disabled" by default and can be enabled in board-specific overlays depending on application needs.
Reference: UG585 Zynq-7000 SoC TRM
Link: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM