serial/uart_ns16550: support cec1702 alternate clock

CEC1702 ns16550 compatible UART has alternate high-speed clock selectable with the high bit of the baud rate divisor register. Signed-off-by: Timo Teräs <[email protected]>
zephyrproject-rtos · Dec 2, 2019 · 1145c19 · 1145c19
1 parent b801c5f
commit 1145c19
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Showing 2 changed files with 11 additions and 2 deletions.
diff --git a/drivers/serial/uart_ns16550.c b/drivers/serial/uart_ns16550.c
@@ -78,6 +78,10 @@ BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
 #define REG_DLF 0xC0  /* Divisor Latch Fraction         */
 #define REG_PCP 0x200 /* PRV_CLOCK_PARAMS (Apollo Lake) */
 
+/* equates for baud rate divisor register */
+
+#define BRD_MCHP_XEC_BAUD_CLK_SEL 0x8000 /* microchip uart: use system clock */
+
 /* equates for interrupt enable register */
 
 #define IER_RXRDY 0x01 /* receiver data ready */
@@ -300,6 +304,11 @@ static void set_baud_rate(struct device *dev, u32_t baud_rate)
 		 */
 		divisor = ((dev_cfg->sys_clk_freq + (baud_rate << 3))
 					/ baud_rate) >> 4;
+#if defined(DT_COMPAT_MICROCHIP_XEC_NS16550)
+		if (dev_cfg->sys_clk_freq == CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
+			divisor |= BRD_MCHP_XEC_BAUD_CLK_SEL;
+		}
+#endif
 
 		/* set the DLAB to access the baud rate divisor registers */
 		lcr_cache = INBYTE(LCR(dev));

diff --git a/dts/arm/microchip/cec1702.dtsi b/dts/arm/microchip/cec1702.dtsi
@@ -28,15 +28,15 @@
 
 	soc {
 		uart0: uart@400f2400 {
-			compatible = "ns16550";
+			compatible = "ns16550", "microchip,xec-ns16550";
 			reg = <0x400f2400 0x400>;
 			interrupts = <40 0>;
 			clock-frequency = <1843200>;
 			label = "UART_0";
 			reg-shift = <0>;
 		};
 		uart1: uart@400f2800 {
-			compatible = "ns16550";
+			compatible = "ns16550", "microchip,xec-ns16550";
 			reg = <0x400f2800 0x400>;
 			interrupts = <41 0>;
 			clock-frequency = <1843200>;