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opentitan
opentitan PublicForked from lowRISC/opentitan
OpenTitan: Open source silicon root of trust
SystemVerilog
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core-v-verif
core-v-verif PublicForked from openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Assembly
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cva6
cva6 PublicForked from openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Assembly
126 contributions in the last year
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Contribution activity
April 2025
Created 3 repositories
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xiaoweish/taxi
SystemVerilog
This contribution was made on Apr 9
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xiaoweish/x-heep
C
This contribution was made on Apr 8
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xiaoweish/cmn-tools
Python
This contribution was made on Apr 5
Opened 1 issue in 1 repository
riscv/riscv-fast-interrupt
1
open
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Reflect Release 0.10 in Documentation?
This contribution was made on Apr 8