Instruction Cache Stages

Cache access takes 3 stages to handle. This is because the cache is designed using block ram modules to store the data as otherwise the whole fpga would just be a cache. The cache is set by default to be 1024 entries deep, have the line size is adjustable via a parameter but is 2 instructions/line for now. The stages are:

1. Access block ram module
2. Capture block ram output to intermediate register
3. Tag compare and send request on a cache miss.

When a cache miss occurs, the outputs of stage 1 will be stored in a temporary register. This is because the when a requested line is fetched, it will be written to the block ram, which means on the subsequent cycle, the output of the ram would be the fetched line. As a result, the miss process looks like this:

1. Miss is found, back up I-cache output, stall the rest. (state transition: no_miss --> miss)
2. Wait for fetched line (state transition: miss --> miss)
3. Fetched line received and inputted into cache, also simultaneously sent to tag compare stage so it can be sent to decode stage next cycle. The backup of the block ram output from before the line was updated will also be forwarded to the register between stages 2/3.

This module is meant to connect directly to a memory arbiter to handle addressing and sending axi4 requests to IP cores which will interface with ddr3 and flash memory.