Honor Pipeline9 bus allowed layers per connection - #2248
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seveibar
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this doesn't make sense- one connection limits the entire node to particular layers?
also why is __allowedZ being made part of the API?
You're hacking on bus routing to Pipeline9 without a plan
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Rewritten from scratch on the real AM62L repro in #2243. The previous first-port/node-wide constraint bug and SRJ |
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This PR has been automatically marked as stale because it has had no recent activity. It will be closed if no further activity occurs. |
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This PR was closed because it has been inactive for 1 day since being marked as stale. |
Stacked on #2243.
Real board failure
The regression is extracted from the AM62L carrier HDMI path and keeps the real
SII9022ACNU -> TPD12S016PWR -> HDMI_001Sthree-point connection.TMDS_D2_Nbelongs to a bus whoseallowedLayersis["top"], but Pipeline 9 previously emitted part of that connection oninner1.The SVG snapshot in #2243 shows the violating inner-layer segment. This PR updates that same snapshot to show the complete connection on
top.Fix
The pre-queue traversal hook is implemented by the standalone,
main-based tscircuit/tiny-hypergraph#173. The dependency pin is a temporary compatibility commit built from current tiny-hypergraphmain, #173, and the two unmerged solver APIs already consumed by the #2243 base (trace-density options and preferred-route preservation). It excludes the obsolete repro fixture and branch ancestry. This does not add a Pipeline 9 stage and does not add an__allowedZfield to SRJ connections.Validation
Known follow-up
The reduced real pair routes correctly. The full eight-member HDMI phase now fails loudly when its current topology requires a single-layer crossing, rather than silently escaping the declared layers. That topology problem is separate from enforcing
allowedLayers.